公开(公告)号：US07256087B1

公开(公告)日：2007-08-14

申请号：US11018422

申请日：2004-12-21

Applicant: Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

Inventor： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

Abstract translation: 在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。 集成电路还包括形成在晶体管上的互连线。 互连线包括吸氢材料，并且可以包括单一材料或材料堆。 互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2 H 2或H 2 O 2），从而提高负偏压温度 晶体管的不稳定性（NBTI）寿命。

公开(公告)号：US07227212B1

公开(公告)日：2007-06-05

申请号：US11021220

申请日：2004-12-23

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  James Hunter ,  Thurman J. Rodgers ,  Mike Bruner ,  Klyoko Ikeuchi

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  James Hunter ,  Thurman J. Rodgers ,  Mike Bruner ,  Klyoko Ikeuchi

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/5227 ,  H01L23/53223 ,  H01L23/53238 ,  H01L28/87 ,  H01L2924/0002 ,  Y10S257/924 ,  H01L2924/00

Abstract: In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.

Abstract translation: 在一个实施例中，牺牲层沉积在基底层上。 牺牲层用于限定随后形成的浮动金属结构。 浮动金属结构可以锚定到基层中。 一旦形成了浮动金属结构，则蚀刻围绕浮动金属结构的牺牲层，以产生将浮动金属结构与基底层分开的单位k介电区域。 unity-k电介质区域还将浮动金属结构与另一个浮动金属结构分离。 在一个实施方案中，使用惰性气体氟化物如二氟化氙来蚀刻多晶硅的牺牲层。

公开(公告)号：US07192867B1

公开(公告)日：2007-03-20

申请号：US10184336

申请日：2002-06-26

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Seurabh Dutta Chowdhury ,  Michal Efrati Fastow

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Seurabh Dutta Chowdhury ,  Michal Efrati Fastow

IPC: H01L21/302

CPC classification number: H01L21/76831 ,  H01L21/76814

Abstract: In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of low-k dielectrics in passivation levels. Low-k dielectrics in passivation levels help lower capacitance on metal lines, thereby reducing RC delay and increasing signal propagation speeds.

Abstract translation: 在一个实施例中，钝化层包括低k电介质。 为了防止低k电介质暴露于空气时吸收水分，低k电介质的暴露部分被间隔物覆盖。 可以理解，这有助于低k电介质在钝化层中的集成。 钝化层中的低k电介质有助于降低金属线路上的电容，从而减少RC延迟并增加信号传播速度。

公开(公告)号：US06835616B1

公开(公告)日：2004-12-28

申请号：US10059823

申请日：2002-01-29

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  James Hunter ,  Thurman J. Rodgers ,  Mike Bruner ,  Klyoko Keuchi

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  James Hunter ,  Thurman J. Rodgers ,  Mike Bruner ,  Klyoko Keuchi

IPC: H01L218242

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/5227 ,  H01L23/53223 ,  H01L23/53238 ,  H01L28/87 ,  H01L2924/0002 ,  Y10S257/924 ,  H01L2924/00

Abstract: In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.

Abstract translation: 在一个实施例中，牺牲层沉积在基底层上。 牺牲层用于限定随后形成的浮动金属结构。 浮动金属结构可以锚定到基层中。 一旦形成了浮动金属结构，则蚀刻围绕浮动金属结构的牺牲层，以产生将浮动金属结构与基底层分开的单位k介电区域。 unity-k电介质区域还将浮动金属结构与另一个浮动金属结构分离。 在一个实施方案中，使用惰性气体氟化物如二氟化氙来蚀刻多晶硅的牺牲层。

公开(公告)号：US06624052B2

公开(公告)日：2003-09-23

申请号：US10200396

申请日：2002-07-22

Applicant: Krishnaswamy Ramkumar ,  Manuj Rathor

Inventor： Krishnaswamy Ramkumar ,  Manuj Rathor

IPC: H01L21425

CPC classification number: H01L29/518 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/324 ,  H01L29/517

Abstract: A method of making a semiconductor structure, includes annealing a structure in a deuterium-containing atmosphere. The structure includes (i) a substrate, (ii) a gate dielectric on the substrate, (iii) a gate on the gate dielectric, (iv) an etch-stop layer on the gate, and (v) an interlayer dielectric on the etch-stop layer.

公开(公告)号：US06555484B1

公开(公告)日：2003-04-29

申请号：US08878728

申请日：1997-06-19

Applicant: Krishnaswamy Ramkumar ,  Hanna Bamnolker

Inventor： Krishnaswamy Ramkumar ,  Hanna Bamnolker

IPC: H01L21265

CPC classification number: H01L21/28185 ,  H01L21/2652 ,  H01L21/2822 ,  Y10S438/911 ,  Y10S438/92 ,  Y10S438/981

Abstract: Two different regions of a semiconductor substrate are implanted with dopants/ions. The implantation may occur though a sacrificial oxide layer disposed over the substrate. Following implantation in one or both regions, the substrate may be annealed and the sacrificial oxide layer removed. An oxide layer is then grown over the implanted regions of the substrate. For some embodiments, the substrate may be implanted with arsenic and/or with phosphorus. Further, the anneal may be performed for approximately 30 to 120 minutes at a temperature between approximately 900° C. and 950° C.

Abstract translation: 用掺杂剂/离子注入半导体衬底的两个不同区域。 注入可以通过设置在衬底上的牺牲氧化层发生。 在一个或两个区域中植入之后，可以对衬底进行退火并去除牺牲氧化物层。 然后在衬底的注入区域上生长氧化物层。 对于一些实施例，衬底可以用砷和/或磷进行注入。 此外，退火可以在约900℃至950℃的温度下进行约30至120分钟。

公开(公告)号：US6033991A

公开(公告)日：2000-03-07

申请号：US939838

申请日：1997-09-29

Applicant: Krishnaswamy Ramkumar ,  Pamela Trammel ,  Sharmin Sadoughi

Inventor： Krishnaswamy Ramkumar ,  Pamela Trammel ,  Sharmin Sadoughi

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L21/302

CPC classification number: H01L21/76202 ,  H01L21/7621 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31662

Abstract: A method of forming a field oxide or an isolation region in a semiconductor die. An oxidation mask layer (over an oxide layer disposed over the substrate) is patterned and subsequently etched, preferably so that the oxidation mask layer may have a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the sidewall of the oxidation mask layer. A field oxide is then grown in the recess using a dry oxidizing atmosphere. The sloped sidewall of the substrate recess effectively moves the face of the exposed substrate away from the edge of the oxidation mask layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and less field oxide thinning. The preferred range of slopes for the substrate sidewall is from approximately 10.degree. to 40.degree. with respect to the oxidation mask layer sidewall.

Abstract translation: 在半导体管芯中形成场氧化物或隔离区域的方法。 对氧化掩模层（位于衬底上方的氧化物层上方）进行构图并随后进行蚀刻，优选地使得氧化掩模层可具有几乎垂直的侧壁。 蚀刻隔离区域中的氧化物层和衬底，以在衬底中形成相对于氧化掩模层的侧壁具有倾斜表面的凹部。 然后使用干燥的氧化气氛将场氧化物生长在凹槽中。 衬底凹槽的倾斜侧壁有效地将暴露的衬底的表面远离氧化掩模层侧壁的边缘移动。 与非倾斜技术相比，氧化似乎从图案化蚀刻的内置偏移开始。 这导致氧化物侵蚀减少和较少的场氧化物稀化。 衬底侧壁的斜率的优选范围相对于氧化掩模层侧壁约为10°至40°。

公开(公告)号：US6004399A

公开(公告)日：1999-12-21

申请号：US784207

申请日：1997-01-15

Applicant: Kaichiu Wong ,  Krishnaswamy Ramkumar ,  Hanna Bamnolker ,  Suraj Puri ,  Rajiv Bhushan ,  David Wong ,  Gary Elmore ,  Raj Mohindra

Inventor： Kaichiu Wong ,  Krishnaswamy Ramkumar ,  Hanna Bamnolker ,  Suraj Puri ,  Rajiv Bhushan ,  David Wong ,  Gary Elmore ,  Raj Mohindra

IPC: B08B3/04 ,  B08B3/10 ,  B08B3/12 ,  H01L21/00 ,  B08B3/08

CPC classification number: H01L21/67057 ,  B08B3/04 ,  B08B3/102 ,  B08B3/12 ,  H01L21/67051 ,  Y10S134/902

Abstract: A method is described for cleaning a semiconductor wafer. The method includes immersing a wafer in a liquid comprising water. The wafer has a front face, a back face, and an edge. The method also includes providing a substantially particle free environment adjacent to the front face and the back face as the liquid is being removed. A step of introducing a carrier gas comprising a cleaning enhancement substance also is included. It is believed that the cleaning enhancement substance dopes any liquid adhered to the front and back faces of the wafer to cause a concentration gradient of the cleaning enhancement substance in the liquid and accelerate removal of the adhered liquid off of the water.

Abstract translation: 描述了一种用于清洁半导体晶片的方法。 该方法包括将晶片浸入包含水的液体中。 晶片具有前表面，后表面和边缘。 该方法还包括当正在除去液体时提供与前表面和背面相邻的基本上无颗粒的环境。 还包括引入包含清洁增强物质的载气的步骤。 相信清洁增强物质会粘附到晶片的正面和背面的任何液体，从而引起液体中清洁增强物质的浓度梯度，并加速从水中除去附着液体。

公开(公告)号：US09716153B2

公开(公告)日：2017-07-25

申请号：US13539459

申请日：2012-07-01

Applicant: Sagy Levy ,  Fredrick Jenne ,  Krishnaswamy Ramkumar

Inventor： Sagy Levy ,  Fredrick Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  H01L29/40 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/408 ,  H01L21/28282 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/792 ,  H01L29/7926

Abstract: Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer.

公开(公告)号：US09431549B2

公开(公告)日：2016-08-30

申请号：US13436875

申请日：2012-03-31

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  B82Y10/00 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/7923 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11578 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/792 ,  H01L29/7926

Abstract: An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

Abstract translation: 描述了非易失性电荷陷阱存储器件的实施例。 在一个实施例中，该装置包括一个通道，该沟道包括覆盖在电连接存储器件的第一扩散区和第二扩散区的衬底上的表面的硅以及与沟道的至少一部分相交并且覆盖的栅极堆，栅极 包括邻接通道的隧道氧化物的堆叠，邻接隧道氧化物的分裂电荷捕获区域和与分离的电荷捕获区域邻接的多层阻挡电介质。 分离电荷捕获区域包括第一电荷捕获层，其包含更接近隧道氧化物的氮化物，以及包含覆盖在第一电荷俘获层上的氮化物的第二电荷俘获层。 多层阻挡电介质至少包括高K电介质层。