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    Error logging for a memory device with on-die wear leveling
    51.
    发明授权
    Error logging for a memory device with on-die wear leveling 有权

    公开(公告)号：US12159039B2

    公开(公告)日：2024-12-03

    申请号：US17731100

    申请日：2022-04-27

    Applicant: Micron Technology, Inc.

    Inventor： Bryan David Kerstetter ,  Donald M. Morgan ,  Alan J. Wilson ,  John David Porter ,  Jeffrey P. Wright

    IPC: G06F3/06

    Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

    Systems and methods for memory cell array initialization
    57.
    发明授权
    Systems and methods for memory cell array initialization 有权

    公开(公告)号：US10127971B1

    公开(公告)日：2018-11-13

    申请号：US15583023

    申请日：2017-05-01

    Applicant: Micron Technology, Inc.

    Inventor： Scott J. Derner ,  Huy T. Vo ,  Patrick Mullarkey ,  Jeffrey P. Wright ,  Michael A. Shore

    IPC: G11C11/4091 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4094 ,  G11C11/4096

    Abstract: Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.

    SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE
    59.
    发明申请
    SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE 有权
    基于命令信号和操作状态解码命令的系统和方法

    公开(公告)号：US20170004872A1

    公开(公告)日：2017-01-05

    申请号：US15265677

    申请日：2016-09-14

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： JEFFERY W. JANZEN ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4076

    CPC classification number: G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

    Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

    Abstract translation: 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

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