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    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    52.
    发明公开
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20240081052A1

    公开(公告)日：2024-03-07

    申请号：US18505563

    申请日：2023-11-09

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John D. Hopkins

    IPC: H10B41/27 ,  H01L21/768 ,  H10B43/27

    CPC classification number: H10B41/27 ,  H01L21/76802 ,  H01L21/76889 ,  H10B43/27

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor tier between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material and comprise metal material. After the horizontally-elongated lines are formed, conductive material is formed in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    53.
    发明公开
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20240074179A1

    公开(公告)日：2024-02-29

    申请号：US17896570

    申请日：2022-08-26

    Applicant: Micron Technology, Inc

    Inventor： John D. Hopkins ,  Damir Fazil ,  Jordan D. Greenlee

    IPC: H01L27/11582 ,  H01L27/11556

    CPC classification number: H01L27/11582 ,  H01L27/11556

    Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The channel material of individual of the channel-material strings is directly electrically coupled to the conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises insulating material. The conductor material in the conductor tier comprises a pair of side interfaces that individually extend downwardly from a top of the conductor tier on one of opposing sides of the intervening material and individually extend longitudinally-along the immediately-laterally-adjacent memory blocks. The side interfaces have the conductor material laterally-over opposing sides thereof. Other embodiments, including method, are disclosed.

    Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    55.
    发明公开
    Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20230422503A1

    公开(公告)日：2023-12-28

    申请号：US18244169

    申请日：2023-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  John D. Hopkins ,  Yongjun Jeff Hu ,  Swapnil Lengade

    IPC: H10B43/27 ,  H01L21/311 ,  H10B41/27

    CPC classification number: H10B43/27 ,  H01L21/31111 ,  H10B41/27

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b). Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-first-tier or said lower upper-first-tier. After the stop, the sacrificial material is removed from the lower channel openings and form channel-material strings in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

    MICROELECTRONIC DEVICES INCLUDING IMPLANT REGIONS, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS
    56.
    发明公开
    MICROELECTRONIC DEVICES INCLUDING IMPLANT REGIONS, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS 审中-公开

    公开(公告)号：US20230397418A1

    公开(公告)日：2023-12-07

    申请号：US17805167

    申请日：2022-06-02

    Applicant: Micron Technology, Inc.

    Inventor： Zhiqiang Teo ,  Chun Wei Ee ,  Anson Lin ,  Yuwei Ma ,  Martin J. Barclay ,  John D. Hopking ,  Jordan D. Greenlee

    IPC: H01L27/11582

    CPC classification number: H01L27/11582

    Abstract: A microelectronic device comprises lateral contact structures overlying a source structure and comprising conductive material, a cap material overlying the lateral contact structures and comprising implant regions therein, a stack structure overlying the cap material and comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers, and pillars vertically extending through the stack structure and into the source structure. The pillars individually comprise semiconductive channel material in physical contact with the lateral contact structures. The microelectronic device comprises filled slot structures vertically extending at least through the stack structure and the cap material. The filled slot structures are positioned within horizontal areas of the implant regions of the cap material. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

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