公开(公告)号：US08349729B2

公开(公告)日：2013-01-08

申请号：US13418716

申请日：2012-03-13

申请人： Karl W. Barth ,  Ricardo A. Donaton ,  Spyridon Galis ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ricardo A. Donaton ,  Spyridon Galis ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L21/4763

CPC分类号： H01L23/5389 ,  H01L21/76898 ,  H01L24/80 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2924/12044

摘要： Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.

摘要翻译： 第一基板和第二基板中的每一个包括具有耐扩散电介质材料如氮化硅的表面。 凹陷区域形成在耐扩散电介质材料中，并且填充有可粘结介电材料。 第一和第二基板中的金属焊盘和可接合的介质材料部分的图案可以具有镜面对称性。 第一和第二基板通过金属焊盘和可接合的介电材料部分之间的触点之间的触点进行物理接触和接合。 通过基底通孔（TSV）结构通过键合介电材料部分形成。 位于TSV结构周围的每对键合的电介质材料部分之间的界面由两个扩散电阻的介电材料层封装，使得接合界面处的金属的扩散被包含在每对键合介电材料部分内。

公开(公告)号：US20120126937A1

公开(公告)日：2012-05-24

申请号：US13296242

申请日：2011-11-15

申请人： Lawrence A. Clevenger ,  Rainer K. Krause ,  Kevin S. Petrarca ,  Carl J. Radens ,  Brian C. Sapp

发明人： Lawrence A. Clevenger ,  Rainer K. Krause ,  Kevin S. Petrarca ,  Carl J. Radens ,  Brian C. Sapp

IPC分类号： G08B29/00

CPC分类号： G08B13/14 ,  G06Q10/087

摘要： Asset management for control of electric appliances comprises a keycode unit and an equipment unit embedded in an appliance. The keycode unit is located in a protected environment and relates to an asset management area. The equipment unit may store an appliance identification code. The keycode unit and the equipment unit may be in communication contact, whereby the equipment unit sends positioning coordinates to the keycode unit, and wherein the equipment unit is adapted to lock the appliance via the lock unit, in response to a lock signal that the equipment unit receives from the keycode unit, if the appliance moves outside the asset management area.

摘要翻译： 用于控制电器的资产管理包括密码单元和嵌入在器具中的设备单元。 键码单元位于受保护的环境中，与资产管理区域有关。 设备单元可以存储设备标识码。 键码单元和设备单元可以是通信接触的，由此设备单元向键码单元发送定位坐标，并且其中设备单元适于经由锁定单元锁定设备，响应于锁定信号，设备 如果设备移动到资产管理区域外，则单元从密钥单元接收。

公开(公告)号：US07638406B2

公开(公告)日：2009-12-29

申请号：US11320375

申请日：2005-12-28

申请人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

发明人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

IPC分类号： H01L21/20

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of forming an inductor. The method includes: forming a dielectric layer on a substrate; forming a lower trench in the dielectric layer; forming a liner in the lower trench and on the dielectric layer; forming a Cu seed layer over the liner; forming a resist layer on the Cu seed layer; forming an upper trench in the resist layer; electroplating Cu to completely fill the lower trench and at least partially fill the upper trench; removing the resist layer; selectively forming a passivation layer on all exposed Cu surfaces; selectively removing the Cu seed layer from regions of the liner; and removing the thus exposed regions of the liner from the dielectric layer, wherein a top surface of the inductor extends above a top surface of the dielectric layer, the passivation layer remaining on regions of sidewalls of the inductor above the top surface of the dielectric layer.

摘要翻译： 一种形成电感器的方法。 该方法包括：在基板上形成电介质层; 在介电层中形成下沟槽; 在下沟槽和电介质层上形成衬垫; 在衬套上形成Cu籽晶层; 在Cu籽晶层上形成抗蚀剂层; 在抗蚀剂层中形成上沟槽; 电镀Cu以完全填充下沟槽并且至少部分地填充上沟槽; 去除抗蚀剂层; 在所有暴露的Cu表面上选择性地形成钝化层; 从所述衬垫的区域选择性地去除所述Cu籽晶层; 以及从所述电介质层去除所述衬垫的这样暴露的区域，其中所述电感器的顶表面延伸到所述电介质层的顶表面之上，所述钝化层保留在所述电介质的位于所述电介质层的顶表面之上的侧壁的区域上 。

公开(公告)号：US07468124B2

公开(公告)日：2008-12-23

申请号：US11382802

申请日：2006-05-11

申请人： Nancy A. Greco ,  Kimberly F. Hooper ,  Kevin S. Petrarca

发明人： Nancy A. Greco ,  Kimberly F. Hooper ,  Kevin S. Petrarca

IPC分类号： C23F13/04

CPC分类号： C23F13/04 ,  H01L21/02063 ,  H01L21/67057

摘要： A method and apparatus for cleaning a wafer with a metal exposed through an insulator, through the use of a wet cleaning tank in concert with a feedback system on the potential difference between two leads of the wet cleaning tank. The cleaning tank has a bath in which the wafer and the two leads are immersed. The potential difference between the two leads is regulated when the feedback system detects a change in the potential across the two leads.

摘要翻译： 一种通过使用湿式清洗槽与反馈系统一起使用通过绝缘子暴露的金属来清洁晶片的方法和装置，该方法和装置关于湿式清洗槽的两根引线之间的电位差。 清洗槽具有浸没晶片和两根引线的槽。 当反馈系统检测到两个引线上的电位变化时，两个引线之间的电位差被调节。

公开(公告)号：US20080156636A1

公开(公告)日：2008-07-03

申请号：US11971488

申请日：2008-01-09

申请人： Kevin S. Petrarca ,  Mahadevaiyer Krishnan ,  Michael Lofaro ,  Kenneth P. Rodbell

发明人： Kevin S. Petrarca ,  Mahadevaiyer Krishnan ,  Michael Lofaro ,  Kenneth P. Rodbell

IPC分类号： C23C14/16

CPC分类号： H01L21/76873 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76877

摘要： Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer. The impure copper seed layer covers a barrier layer, which covers an insulating layer that has an opening. Electroplated copper fills the opening in the insulating layer. Through a chemical mechanical polish, the barrier layer, the impure an impure copper seed layer derived from an electroplated copper bath copper seed layer, and the electroplated copper are planarized to the insulating layer.

摘要翻译： 通过包括不纯铜种子层的互连可以减轻线半导体器件后端的铜互连边缘的缺陷。 不纯铜种子层覆盖阻挡层，其覆盖具有开口的绝缘层。 电镀铜填充绝缘层中的开口。 通过化学机械抛光，阻挡层，不纯的由电镀铜浴铜籽晶层衍生的铜籽晶层和电镀铜平坦化到绝缘层。

公开(公告)号：US20070275552A1

公开(公告)日：2007-11-29

申请号：US11420253

申请日：2006-05-25

申请人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Vidhya Ramachandran ,  Theodorus E. Standaert

发明人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Vidhya Ramachandran ,  Theodorus E. Standaert

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.

摘要翻译： 半导体结构包括形成在层间电介质（ILD）层内的多个导电线和形成在ILD层和导电线之上的非平面覆盖层，其中覆盖层相对于导电线在第 导线。

公开(公告)号：US07273806B2

公开(公告)日：2007-09-25

申请号：US10905013

申请日：2004-12-09

申请人： Robert A. Groves ,  Peter A. Gruber ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

发明人： Robert A. Groves ,  Peter A. Gruber ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L21/44

CPC分类号： H05K3/3468 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01066 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H05K3/325 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/128 ,  H05K2203/162 ,  H05K2203/167 ,  H01L2224/0401

摘要： Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.

摘要翻译： 公开了在封装之前在基板上形成导电结构的方法和根据该方法生成的测试探针结构。 导电结构包括通过注射成型的焊料形成的高纵横比结构。 本发明可以应用于在典型的BEOL之后以及在封装之前在常规半导体衬底上形成无源元件和互连。 该方法可以为导电结构提供更好的电迁移特性，较低的电阻率和更高的Q因子。 此外，该方法可以向后兼容并可定制。

公开(公告)号：US06825075B2

公开(公告)日：2004-11-30

申请号：US10757214

申请日：2004-01-14

申请人： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

发明人： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

IPC分类号： H01L218242

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/7684 ,  H01L28/60

摘要： A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening. The dielectric layer and the additional layer are planarized, preferably by CMP.

摘要翻译： 描述了一种在衬底中形成的特征中制造封装金属结构的方法。 特征的侧壁和底部被阻挡层覆盖，并且该特征被金属填充，优选地通过电镀。 在金属中形成凹部，并且沉积附加的阻挡层，覆盖金属的顶表面并与第一阻挡层接触。 优选通过化学机械抛光将附加阻挡层平坦化。 该方法可用于制造MIM电容器，其中封装的金属结构用作电容器的下板。 第二衬底层沉积在衬底的顶表面上，具有覆盖封装的金属结构的开口。 介电层沉积在开口中，覆盖其底部的封装金属结构。 作为电容器的上板的附加层被沉积以覆盖电介质层并填充开口。 介电层和附加层优选通过CMP平坦化。

公开(公告)号：US06613641B1

公开(公告)日：2003-09-02

申请号：US09764834

申请日：2001-01-17

申请人： Richard P. Volant ,  John M. Cotte ,  Kevin S. Petrarca ,  Kenneth J. Stein

发明人： Richard P. Volant ,  John M. Cotte ,  Kevin S. Petrarca ,  Kenneth J. Stein

IPC分类号： H01L218238

CPC分类号： H01L28/40 ,  H01L21/31687 ,  Y10S438/957

摘要： Metal-insulator-metal capacitor structures are formed in semiconductor substrates using an anodization procedure on deposited underlying metalization followed by deposition of the second metal and planarization by chemical-mechanical polishing or other procedures. The process is additive in character, as opposed to traditional subtractive etch processes for forming capacitor structures. In addition, the process can be used in damascene applications, and can be used to form a wide variety of capacitive structures while reducing the number of mask layers required for formation.

公开(公告)号：US06534863B2

公开(公告)日：2003-03-18

申请号：US09781121

申请日：2001-02-09

申请人： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

发明人： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

IPC分类号： H01L2348

CPC分类号： H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.