公开(公告)号：US06534863B2

公开(公告)日：2003-03-18

申请号：US09781121

申请日：2001-02-09

申请人： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

发明人： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

IPC分类号： H01L2348

CPC分类号： H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

公开(公告)号：US07273806B2

公开(公告)日：2007-09-25

申请号：US10905013

申请日：2004-12-09

申请人： Robert A. Groves ,  Peter A. Gruber ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

发明人： Robert A. Groves ,  Peter A. Gruber ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L21/44

CPC分类号： H05K3/3468 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01066 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H05K3/325 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/128 ,  H05K2203/162 ,  H05K2203/167 ,  H01L2224/0401

摘要： Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.

摘要翻译： 公开了在封装之前在基板上形成导电结构的方法和根据该方法生成的测试探针结构。 导电结构包括通过注射成型的焊料形成的高纵横比结构。 本发明可以应用于在典型的BEOL之后以及在封装之前在常规半导体衬底上形成无源元件和互连。 该方法可以为导电结构提供更好的电迁移特性，较低的电阻率和更高的Q因子。 此外，该方法可以向后兼容并可定制。

公开(公告)号：US06362557B1

公开(公告)日：2002-03-26

申请号：US09649486

申请日：2000-08-28

申请人： Peter A. Gruber ,  Frederic Maurer ,  George F. Walker

发明人： Peter A. Gruber ,  Frederic Maurer ,  George F. Walker

IPC分类号： H01L4108

CPC分类号： H01L41/0906

摘要： An actuator scaled to macroscopic or microscopic sizes, uses ultrasonic energy to induce motion of an object in a desired direction. The actuator includes one or more pair of piezoelectric transducers connected with a transducer tip. Supplying the piezoelectric transducers with alternating current electrical power causes the tip to vibrate at ultrasonic frequencies. Urging the vibrating tip into contact with a surface on the object at a selected angle of inclination induces the object to move in the desired direction at a rate determined by the inclination angle. Multiple actuators can be used to induce a fall range of movements of variously shaped objects. In microscopic form, the actuator can be used to create a MEMS device. The optional application of a compliant material either on the transducer tip or on the object's surface enhances the movement induced by the actuator.

摘要翻译： 按照宏观或微观尺寸的致动器，使用超声波能量来诱导物体沿所需方向的运动。 致动器包括与换能器尖端连接的一对或多对压电换能器。 为具有交流电功率的压电换能器提供使尖端以超声频率振动。 将振动尖端以选定的倾斜角度与物体上的表面接触，使得物体以由倾斜角确定的速率在所需方向上移动。 可以使用多个致动器来引起各种形状物体的运动的下降范围。 在微观形式中，致动器可用于创建MEMS装置。 在换能器尖端或物体表面上可选地应用柔性材料增强了由致动器引起的运动。

公开(公告)号：US06656750B1

公开(公告)日：2003-12-02

申请号：US09301889

申请日：1999-04-29

申请人： Madhav Datta ,  Peter A. Gruber ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  George F. Walker

发明人： Madhav Datta ,  Peter A. Gruber ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  George F. Walker

IPC分类号： G01R3126

CPC分类号： H01L24/13 ,  B23K1/0016 ,  B23K1/20 ,  B23K2101/36 ,  G01R31/2886 ,  H01L22/00 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1148 ,  H01L2224/1184 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3436 ,  H01L2924/00014

摘要： A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than ½ of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders. When the MSS method is used for planting the bumps, solder bumps are transferred onto the wafer surface in a substantially flattened hemi-spherical shape.

摘要翻译： 公开了一种在平坦焊料凸块上测试集成电路芯片的方法以及配备有平坦焊料凸块的IC芯片。 在该方法中，首先提供具有多个接合焊盘和多个平坦焊料凸块的IC芯片，其中每个焊料凸块在多个焊盘上具有小于其直径的1/2的高度。 因此，探针线可以容易地用于接触焊料凸块上的增加的目标区域，以建立与测试电路的电连接。 探针可以容易地进行，凸块的所有Z高度基本相等。 焊料凸块的高度可以通过平面化处理来适当地控制，其中软焊料凸块被平面表面压缩，或者通过用于形成焊料凸块的MSS或电镀工艺在原位模具中形成焊料凸块 呈短圆柱形。 当使用MSS方法种植凸块时，焊料凸块以大致平坦的半球形转移到晶片表面上。

公开(公告)号：US08828860B2

公开(公告)日：2014-09-09

申请号：US13600204

申请日：2012-08-30

申请人： Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

发明人： Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

IPC分类号： H01L21/00

CPC分类号： H05K3/3436 ,  B23K1/0016 ,  B23K3/0638 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/11011 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81065 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/14 ,  H01L2924/20104 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/35 ,  H05K3/3494 ,  H05K13/0465 ,  H05K2203/043 ,  H01L2924/00014 ,  H01L2924/014

摘要： Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly.

摘要翻译： 采用多次注入熔融焊料来形成双层焊料凸点，其外层在比其内部部分更低的温度下熔化。 在倒装芯片组装过程中，回流温度高于外层的熔化温度并低于焊料凸块的内部部分的熔化温度。 由于焊料凸块的内部在回流期间不会塌陷，所以可以在相对低的温度下制造倒装芯片组件并具有高的间隔高度。 具有双重焊料凸块的结构有助于倒装芯片组装。

公开(公告)号：US20140065771A1

公开(公告)日：2014-03-06

申请号：US13600204

申请日：2012-08-30

申请人： Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

发明人： Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

IPC分类号： H01L21/60

CPC分类号： H05K3/3436 ,  B23K1/0016 ,  B23K3/0638 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/11011 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81065 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/14 ,  H01L2924/20104 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/35 ,  H05K3/3494 ,  H05K13/0465 ,  H05K2203/043 ,  H01L2924/00014 ,  H01L2924/014

摘要： Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly.

公开(公告)号：US08381962B2

公开(公告)日：2013-02-26

申请号：US13025419

申请日：2011-02-11

申请人： Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah ,  Kazushige Toriyama

发明人： Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah ,  Kazushige Toriyama

IPC分类号： B23K1/00 ,  B23K37/00

CPC分类号： B23K3/0638 ,  B23K1/0016

摘要： A flexible unitary mask has a plurality of through holes. A substrate has a plurality of wettable pads in recessed regions defining volumes. The through holes are aligned with the wettable pads. Molten solder is directly injected through the through holes of the flexible unitary mask into the volumes with the wettable pads, such that the through holes and the volumes with the wettable pads are filled with solder. The solder is allowed to solidify, forming a plurality of solder structures adhered to the wettable pads. The flexible unitary mask is peeled from the substrate after the solder has solidified.

摘要翻译： 柔性酉面具有多个通孔。 衬底在限定体积的凹陷区域中具有多个可湿性垫。 通孔与可湿性垫对齐。 熔融的焊料通过柔性整体式掩模的通孔被直接注入到具有可湿性垫的体积中，使得通孔和具有可湿性垫的体积被焊料填充。 允许焊料固化，形成粘附到可湿性垫的多个焊料结构。 焊料固化后，将柔性单位掩模从基板上剥离。

公开(公告)号：US08376207B2

公开(公告)日：2013-02-19

申请号：US13367466

申请日：2012-02-07

申请人： Stephen L. Buchwalter ,  Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

发明人： Stephen L. Buchwalter ,  Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

IPC分类号： B23K5/00 ,  B23K20/08 ,  B22D41/00

CPC分类号： B23K3/0638 ,  B23K3/08 ,  B23K2101/42 ,  H01L21/4853 ,  H01L24/11 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K1/111 ,  H05K3/3457 ,  H05K2201/09472 ,  H05K2203/0126 ,  Y10T29/49826 ,  Y10T156/1062 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A portion of compliant material includes four walls defining a slot. The slot has a relatively large cross-section end in fluid communication with a solder reservoir, and also has a relatively small cross-section end opposed to the relatively large cross-section end. The slot has a generally elongate rectangular shape when viewed in plan, with a length perpendicular to a scan direction, a width, parallel to the scan direction, associated with the relatively large cross section end, and a width, parallel to the scan direction, associated with the relatively small cross section end. The slot is configured in the portion of compliant material such that the relatively small cross-section end of the slot normally remains substantially closed, but locally opens sufficiently to dispense solder from the reservoir when under fluid pressure and locally unsupported by a workpiece. Methods of operation and fabrication are also disclosed.

摘要翻译： 柔性材料的一部分包括限定槽的四个壁。 狭槽具有与焊料储存器流体连通的相对较大的横截面端，并且还具有与相对大的横截面端相对的相对较小的横截面端。 当在平面中观察时，狭槽具有大致细长的矩形形状，其垂直于扫描方向的长度，与扫描方向平行的宽度，与相对大的横截面端相关联，并且平行于扫描方向的宽度， 与相对较小的截面端相关联。 狭槽配置在柔性材料的部分中，使得狭槽的相对小的横截面端部通常保持基本上闭合，但是当处于流体压力下并且局部地不被工件支撑时，局部开口足够地从储存器分配焊料。 还公开了操作和制造方法。

公开(公告)号：US20120234902A1

公开(公告)日：2012-09-20

申请号：US13487378

申请日：2012-06-04

申请人： S. Jay Chey ,  David Danovitch ,  Peter A. Gruber ,  Cornelia K. Tsang

发明人： S. Jay Chey ,  David Danovitch ,  Peter A. Gruber ,  Cornelia K. Tsang

IPC分类号： B23K31/02 ,  B23K3/06

CPC分类号： B23K1/0016 ,  B23K3/0638 ,  B23K2101/40

摘要： A plurality of through-substrate holes is formed in each of at least one substrate. Each through-substrate hole extends from a top surface of the at least one substrate to the bottom surface of the at least one substrate. The at least one substrate is held by a stationary chuck or a rotating chuck. Vacuum suction is provided to a set of through-substrate holes among the plurality of through-substrate holes through a vacuum manifold attached to the bottom surface of the at least one substrate. An injection mold solder head located above the top surface of the at least one substrate injects a solder material into the set of through-substrate holes to form a plurality of through-substrate solders that extend from the top surface to the bottom surface of the at least one substrate. The vacuum suction prevents formation of air bubbles or incomplete filling in the plurality of through-substrate holes.

摘要翻译： 在至少一个基板中的每一个中形成多个贯通基板孔。 每个贯穿基板孔从至少一个基板的顶表面延伸到至少一个基板的底表面。 至少一个基板由固定卡盘或旋转卡盘保持。 通过安装在至少一个基板的底面上的真空歧管，将多个通孔基板孔内的一组贯通基板孔提供真空抽吸。 位于至少一个衬底的顶表面上方的注射模具焊头将焊料材料注入到一组通孔衬底孔中，以形成从顶表面延伸到底表面的多个通孔衬底焊料 至少一个底物。 真空吸力防止在多个贯通基板孔中形成气泡或不完全填充。

公开(公告)号：US20120138769A1

公开(公告)日：2012-06-07

申请号：US13371840

申请日：2012-02-13

申请人： Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

发明人： Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

IPC分类号： B22C9/22

CPC分类号： B23K1/0016 ,  B23K3/0623 ,  B23K2101/40 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/29099 ,  H01L2924/00

摘要： Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

摘要翻译： 通过执行几个步骤在晶片的附接点上形成互连。 在半导体衬底中形成具有预定形状的多个空腔。 然后用互连材料填充这些空腔以形成互连。 互连随后连接到晶片的附接点。