公开(公告)号：US07168016B2

公开(公告)日：2007-01-23

申请号：US09823926

申请日：2001-03-30

申请人： Giovanni Campardo ,  Stefano Commodaro ,  Massimiliano Picca ,  Patrizia Mongelli

发明人： Giovanni Campardo ,  Stefano Commodaro ,  Massimiliano Picca ,  Patrizia Mongelli

IPC分类号： G11C29/00

CPC分类号： G11C29/56

摘要： A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.

摘要翻译： 一种方法和控制装置用于测试电子存储器件。 该方法包括将测试数据和/或指令加载到与存储器单元和集成存储电路的矩阵阵列相关联的控制逻辑电路部分中。 根据本发明，临时使用测试操作控制装置而不是控制逻辑，测试操作控制装置可以拆卸地外部并连接到存储装置。 有利地，测试操作控制设备是存储器外部的矩阵单元阵列。

公开(公告)号：US08958242B2

公开(公告)日：2015-02-17

申请号：US13101322

申请日：2011-05-05

申请人： Gian Pietro Vanalli ,  Stefano Corno ,  Giovanni Campardo ,  Angelo Visconti ,  Silvia Beltrami ,  Alexey Petrushin

发明人： Gian Pietro Vanalli ,  Stefano Corno ,  Giovanni Campardo ,  Angelo Visconti ,  Silvia Beltrami ,  Alexey Petrushin

IPC分类号： G11C11/34 ,  H05B3/00 ,  G11C11/00 ,  G11C16/34 ,  H01L23/34

CPC分类号： G11C16/26 ,  G11C11/00 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  H01L23/345 ,  H01L2924/0002 ,  H05B3/00 ,  H01L2924/00

摘要： A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.

摘要翻译： 存储器控制器可以向闪存中的加热器提供电流以减少循环引起的误差。 如果需要，加热后，可以刷新存储器。 在非电池供电系统中，数据可能在加热之前从存储器中移除，并在加热后恢复到存储器。

公开(公告)号：US20140015560A1

公开(公告)日：2014-01-16

申请号：US13548004

申请日：2012-07-12

申请人： Giovanni Campardo ,  Flavio Maggioni ,  Riccardo Liberini

发明人： Giovanni Campardo ,  Flavio Maggioni ,  Riccardo Liberini

IPC分类号： G01R1/073

CPC分类号： G01R1/07378

摘要： An interface board of a testing head for a test equipment of electronic devices is described. The testing head includes a plurality of contact probes, each contact probe having at least one contact tip suitable to abut against contact pads of a device to be tested, as well as a contact element for the connection with a board of the test equipment. Suitably, the interface board comprises a substrate and at least one redirecting die housed on a first surface of that substrate and a plurality of contact pins projecting from a second surface of that substrate opposed to the first surface. The redirecting die includes at least one semiconductor substrate whereon at least a first plurality of contact pads is realized, suitable to contact a contact element of a contact probe of the testing head, the contact pins being suitable to contact the board.

摘要翻译： 描述了用于电子设备的测试设备的测试头的接口板。 测试头包括多个接触探针，每个接触探针具有至少一个适于邻接待测试装置的接触垫的接触尖端，以及用于与测试设备的板连接的接触元件。 适当地，接口板包括衬底和容纳在该衬底的第一表面上的至少一个重定向模具和从该衬底的与第一表面相对的第二表面突出的多个接触针。 重定向管芯包括至少一个半导体衬底，其中至少第一多个接触焊盘被实现，适于接触测试头的接触探针的接触元件，接触针适于接触该板。

公开(公告)号：US08458562B1

公开(公告)日：2013-06-04

申请号：US12346015

申请日：2008-12-30

申请人： Giovanni Campardo ,  Stefano Corno ,  Gian Pietro Vanalli ,  Manuela Scognamiglio ,  Danilo Caraccio ,  Federico Tiziani ,  Massimiliano Magni ,  Andrea Ghilardelli

发明人： Giovanni Campardo ,  Stefano Corno ,  Gian Pietro Vanalli ,  Manuela Scognamiglio ,  Danilo Caraccio ,  Federico Tiziani ,  Massimiliano Magni ,  Andrea Ghilardelli

IPC分类号： G11C29/42 ,  G11C29/54

CPC分类号： G11C29/42 ,  G06F11/1048 ,  G11C2029/0411

摘要： Embodiments for providing improved reliability or extended life for a non-volatile memory component may comprise a secondary non-volatile memory component to store error correction information, for example.

摘要翻译： 用于为非易失性存储器组件提供改进的可靠性或延长使用寿命的实施例可以包括例如存储纠错信息的次级非易失性存储器组件。

公开(公告)号：US20100318877A1

公开(公告)日：2010-12-16

申请号：US12482400

申请日：2009-06-10

申请人： Paolo Amato ,  Giovanni Campardo

发明人： Paolo Amato ,  Giovanni Campardo

IPC分类号： H03M13/29 ,  H03M13/11 ,  G06F11/10

CPC分类号： H03M13/05 ,  G11C2029/0411 ,  H03M13/15 ,  H03M13/152 ,  H03M13/256 ,  H03M13/27 ,  H03M13/29 ,  H03M13/2933 ,  H03M13/2936 ,  H03M13/41

摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.

摘要翻译： 本公开的实施例提供了与具有纠错的多级编码相关的方法，系统和装置。 在一些实施例中，可以使用级联的编码/解码方案从非易失性存储器单元的矩阵中编程和/或读取数据。 在一些实施例中，计算模块可以确定非易失性存储器件的给定参数组合的每个单元值的实际位数。 可以描述和要求保护其他实施例。

公开(公告)号：US20100032834A1

公开(公告)日：2010-02-11

申请号：US12537075

申请日：2009-08-06

申请人： Gian Pietro Vanalli ,  Giovanni Campardo ,  Aldo Losavio ,  Paolo Pulici ,  Pier Paolo

发明人： Gian Pietro Vanalli ,  Giovanni Campardo ,  Aldo Losavio ,  Paolo Pulici ,  Pier Paolo

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L24/06 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/10126 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13186 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method for manufacturing solder bumps for through vias in a substrate having a first surface and a second surface opposed to each other. The method includes the steps of forming a blind hole extending in the substrate from the first surface for each via and filling each blind hole with a conductive filler; a deepest part of each filler includes a bump portion made of a solder material. The method further includes the step of removing a part of the substrate extending from the second surface to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding bump.

摘要翻译： 一种用于制造具有彼此相对的第一表面和第二表面的基板中的通孔的焊料凸块的方法。 该方法包括以下步骤：从每个通孔的第一表面形成在基板中延伸的盲孔，并用导电填料填充每个盲孔; 每个填料的最深部分包括由焊料材料制成的凸起部分。 所述方法还包括从所述第二表面移除所述基板的一部分以至少具有从所述基板突出的凸起部的步骤。 每个填料的非突出部分限定相应的通孔，凸起部分限定相应的凸块。

公开(公告)号：US20080278923A1

公开(公告)日：2008-11-13

申请号：US12116852

申请日：2008-05-07

申请人： Aldo Losavio ,  Giovanni Campardo ,  Stefano Ricciardi

发明人： Aldo Losavio ,  Giovanni Campardo ,  Stefano Ricciardi

IPC分类号： H05K1/14

CPC分类号： H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic system adapted to perform a corresponding function and including at least a first subsystem and a second subsystem, the first subsystem and the second subsystem being operatively couplable to each other through a plurality of electric connections to perform the function of the system, in which the first subsystem and the second subsystem are respectively integrated on a first material chip and on a second material chip, the plurality of electric connections including a plurality of conductive through holes formed in at least one of the first and second chips and adapted to form a corresponding plurality of inter-chip electric connections when the first and the second chips are superimposed.

摘要翻译： 一种适于执行相应功能并且至少包括第一子系统和第二子系统的电子系统，所述第一子系统和所述第二子系统通过多个电连接可操作地彼此耦合以执行所述系统的功能，其中 第一子系统和第二子系统分别集成在第一材料芯片上并且在第二材料芯片上，多个电连接包括形成在第一和第二芯片中的至少一个芯片中的多个导电通孔，并且适于形成 当第一和第二芯片叠加时相应的多个芯片间电连接。

公开(公告)号：US5793676A

公开(公告)日：1998-08-11

申请号：US649857

申请日：1996-05-03

申请人： Lorenzo Bedarida ,  Giovanni Campardo ,  Giuseppe Fusillo ,  Andrea Silvagni

发明人： Lorenzo Bedarida ,  Giovanni Campardo ,  Giuseppe Fusillo ,  Andrea Silvagni

IPC分类号： G11C8/12 ,  G11C16/08 ,  G11C11/34

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A memory array is divided, at the design stage, into a plurality of elementary sectors; depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors of desired size and number; a correlating unit memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address is supplied to the correlating unit which provides for addressing the elementary sectors associated with the addressed composite sector on the basis of the memorized correlation table.

公开(公告)号：US5633822A

公开(公告)日：1997-05-27

申请号：US458346

申请日：1995-06-02

申请人： Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

发明人： Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/02

CPC分类号： G11C16/04 ,  G11C16/0416 ,  G11C16/30

摘要： A method for writing cells in a memory which reduces errors caused by depleted memory array cells being turned on even when not selected. In the method, nonselected bit lines and nonselected word lines are biased so that the threshold voltage of the nonselected cells increases. In particular, the nonselected bit lines are left floating and the nonselected word lines are set to a zero voltage. Appropriate potentials are applied to the selected word line, selected bit line, and selected source line in order to program the selected cell.

摘要翻译： 一种用于将存储器中的单元写入的方法，其减少由耗尽的存储器阵列单元导致的错误，即使在未选择的情况下也被导通。 在该方法中，非选择位线和非选择字线被偏置，使得非选择单元的阈值电压增加。 特别地，非选定的位线保持浮动，并且非选择的字线被设置为零电压。 适当的电位被施加到所选择的字线，所选位线和所选择的源极线以便对所选择的单元进行编程。

公开(公告)号：US09069015B2

公开(公告)日：2015-06-30

申请号：US13548004

申请日：2012-07-12

申请人： Giovanni Campardo ,  Flavio Maggioni ,  Riccardo Liberini

发明人： Giovanni Campardo ,  Flavio Maggioni ,  Riccardo Liberini

IPC分类号： G01R1/073

CPC分类号： G01R1/07378

摘要： An interface board of a testing head for a test equipment of electronic devices is described. The testing head includes a plurality of contact probes, each contact probe having at least one contact tip suitable to abut against contact pads of a device to be tested, as well as a contact element for the connection with a board of the test equipment. Suitably, the interface board comprises a substrate and at least one redirecting die housed on a first surface of that substrate and a plurality of contact pins projecting from a second surface of that substrate opposed to the first surface. The redirecting die includes at least one semiconductor substrate whereon at least a first plurality of contact pads is realized, suitable to contact a contact element of a contact probe of the testing head, the contact pins being suitable to contact the board.

摘要翻译： 描述了用于电子设备的测试设备的测试头的接口板。 测试头包括多个接触探针，每个接触探针具有至少一个适于邻接待测试装置的接触垫的接触尖端，以及用于与测试设备的板连接的接触元件。 适当地，接口板包括衬底和容纳在该衬底的第一表面上的至少一个重定向模具和从该衬底的与第一表面相对的第二表面突出的多个接触针。 重定向管芯包括至少一个半导体衬底，其中至少第一多个接触焊盘被实现，适于接触测试头的接触探针的接触元件，接触针适于接触该板。