公开(公告)号：US08519644B1

公开(公告)日：2013-08-27

申请号：US13585833

申请日：2012-08-15

申请人： Kim L. Hailey ,  Robert O. Conn

发明人： Kim L. Hailey ,  Robert O. Conn

IPC分类号： H04H7/00

CPC分类号： H05H7/00 ,  H01L24/01 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05H7/06 ,  H05H9/00 ,  H05H15/00 ,  H01L2924/00

摘要： An accelerator assembly includes a first chip and a second chip. An acceleration channel is formed into a surface of a first side of the first chip. The first side of the first chip is covalently bonded to a first side of the second chip such that the channel is a tubular void between the first and second chips. The channel has a tubular inside sidewall surface, substantially no portion of which is a metal surface. The channel has length-to-width ratio greater than five, and a channel width less than one micron. There are many substantially identical channels that extend in parallel between the first and second chips. In one specific example, the assembly is part of a Direct Write On Wafer (DWOW) printing system. The DWOW printing system is useful in semiconductor processing in that it can direct write an image onto a 300 mm diameter wafer in one minute.

摘要翻译： 加速器组件包括第一芯片和第二芯片。 加速通道形成在第一芯片的第一侧的表面上。 第一芯片的第一侧共价键合到第二芯片的第一侧，使得通道是第一和第二芯片之间的管状空隙。 通道具有管状内侧壁表面，其基本上没有其一部分是金属表面。 通道的长宽比大于5，通道宽度小于1微米。 在第一和第二芯片之间并行延伸有许多基本相同的通道。 在一个具体示例中，组件是直接写入晶圆（DWOW）打印系统的一部分。 DWOW打印系统在半导体处理中是有用的，因为它可以在一分钟内直接将图像写入到300mm直径的晶片上。

公开(公告)号：US08062968B1

公开(公告)日：2011-11-22

申请号：US12487855

申请日：2009-06-19

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： H01L21/00

CPC分类号： H01L23/055 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1624 ,  H01L2224/16265 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10S257/924 ,  H01L2924/00

摘要： A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.

摘要翻译： 电容插入器（caposer）设置在芯片与封装的内表面之间的集成电路封装内。 钳口内的导电层构成旁路电容器。 在通孔捕获器中，裸片上的微型凸块通过钳口中的通孔并与封装上相应的着陆焊盘接触。 当电容和接地微型突起通过电容器时，接触旁路电容器的电极。 在通孔容量中，芯片上的电源和接地微型突起通过电源和接地通孔连接到封装上的电源和接地焊盘以及旁路电容器的板。 在信号再分配电容器中，钳位器内的导体在管芯微突起和封装着陆焊盘之间重新分配信号。 在阻抗匹配钳位器中，钳位器内的端接结构为印刷电路板迹线提供阻抗匹配。

公开(公告)号：US20110266034A1

公开(公告)日：2011-11-03

申请号：US13135510

申请日：2011-07-07

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： H05K1/02 ,  H01L21/28

CPC分类号： H05K7/20927 ,  H01L23/473 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/0557 ,  H01L2224/29101 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/00 ,  H01L2224/05552

摘要： An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigaPascals (gPa) and the soft dielectric has a hardness of less than three gPa. The tube of soft dielectric and the metal conductor are both embedded within the volume of insulator. The tube defines a central volume and the metal conductor extends in a direction through the central volume for a distance of at least one inch. The metal conductor is encircled by the soft dielectric when the apparatus is viewed in a cross-sectional plane perpendicular to the direction. The metal conductor may include a plurality of bend portions. The metal conductor does not break when the apparatus is temperature cycled over a range from zero to eighty five degrees Celsius.

摘要翻译： 一种装置包括设置在半导体衬底的顶表面上的绝缘体体积，软电介质管和金属导体。 绝缘体具有大于约3千兆帕（gPa）的硬度，软电介质具有小于3gPa的硬度。 软电介质管和金属导体都嵌入在绝缘体的体积内。 管限定中心体积，并且金属导体沿着穿过中心体积的方向延伸至少一英寸的距离。 当在垂直于该方向的横截面中观察装置时，金属导体被软电介质环绕。 金属导体可以包括多个弯曲部分。 当设备在零度至摄氏度摄氏八十度的范围内温度循环时，金​​属导体不会断裂。

公开(公告)号：US07978029B2

公开(公告)日：2011-07-12

申请号：US12387873

申请日：2009-05-09

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： H01P3/08

CPC分类号： H01P3/08

摘要： A multiple-layer signal conductor has increased surface area for mitigation of skin effect. Parallel extending elongated strips of conductive material are placed in parallel layers and are separated by a thin layer of dielectric. The elongated strips are conductively connected to one another by regularly spaced vias such that a single signal conductor with multiple conductive layers is formed. During high-speed signaling, the skin effect causes current to concentrate near the surfaces of conductors. The multiple-layer signal conductor, however, has increased surface area with respect to its total cross-sectional area. The effective cross-sectional area which is conductive during high-speed signaling is therefore increased, leading to positive effects on transmission line resistance, heating, signal integrity and signal propagation delay. The multiple-layer signal conductor sees special use on silicon circuit boards and can conduct signals at ten gigahertz or greater for distances of up to five inches without rebuffering or termination.

摘要翻译： 多层信号导体具有增加的表面积，以减轻皮肤效应。 平行延伸的细长导电材料条被放置成平行的层并且被薄的电介质隔开。 细长带通过规则间隔的通孔彼此导电连接，从而形成具有多个导电层的单个信号导体。 在高速信号传递期间，皮肤效应导致电流集中在导体表面附近。 然而，多层信号导体相对于其总横截面面积增加了表面积。 因此，在高速信号传导期间导通的有效截面面积增加，导致对传输线电阻，加热，信号完整性和信号传播延迟的积极影响。 多层信号导体在硅电路板上特别使用，并且可以以10千兆赫或更大的距离传输高达五英寸的距离，而无需重新制止或终止。

公开(公告)号：US07764498B2

公开(公告)日：2010-07-27

申请号：US11975011

申请日：2007-10-16

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： H05K7/20

CPC分类号： H05K7/20927 ,  H01L23/473 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/0557 ,  H01L2224/29101 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/00 ,  H01L2224/05552

摘要： A reconfigurable high performance computer occupies less than 360 cubic inches and has an approximate compute power of 0.7 teraflops per second while consuming less than 1000 watts. The computer includes a novel stack of semiconductor substrate assemblies. Some semiconductor substrate assemblies involve field programmable gate array (FPGA) dice that are directly surface mounted, as bare die, to a semiconductor substrate. Other semiconductor substrate assemblies of the stack involve bare memory integrated circuit dice that are directly surface mounted to a semiconductor substrate. Elastomeric connectors interconnect adjacent semiconductor substrates proceeding down the stack. Tines of novel comb-shaped power bus bar assembly structures extend into the stack to supply DC supply voltages. The supply voltages are supplied from bus bars, through vias in the semiconductor substrates, and to the integrated circuits on the other side of the substrates. The power bus bars also serve as capacitors and guides for liquid coolant.

摘要翻译： 可重新配置的高性能计算机占用小于360立方英寸，并且具有每秒0.7 teraflops的近似计算能力，同时消耗少于1000瓦特。 该计算机包括一组新的半导体衬底组件。 一些半导体衬底组件涉及作为裸芯片直接表面安装到半导体衬底的现场可编程门阵列（FPGA）裸片。 堆叠的其他半导体衬底组件包括直接表面安装到半导体衬底的裸存储器集成电路裸片。 弹性连接器将相邻的半导体衬底互相连接，沿堆叠进入。 新颖的梳状电源母线组合结构的齿条延伸到堆叠中以提供直流电源电压。 电源电压由母线，半导体衬底中的通孔以及衬底另一侧的集成电路提供。 电力母线还用作液体冷却剂的电容器和导轨。

公开(公告)号：US07581124B1

公开(公告)日：2009-08-25

申请号：US11326542

申请日：2006-01-04

申请人： Neil G. Jacobson ,  Matthew T. Murphy ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

发明人： Neil G. Jacobson ,  Matthew T. Murphy ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC分类号： G06F1/22

CPC分类号： G11C5/14 ,  G11C5/148 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0401 ,  H03K19/17784

摘要： A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.

摘要翻译： PLD包括多个逻辑块，测试电路和测试引脚组。 逻辑块耦合到选通电路，门电路响应于控制信号选择性地调整块的工作电压。 在PLD的操作期间，响应于通过测试引脚设置到PLD的外部产生的信号来更新控制信号，并使用测试电路将其传送到逻辑块。

公开(公告)号：US20090080158A1

公开(公告)日：2009-03-26

申请号：US11975011

申请日：2007-10-16

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： H05K7/20 ,  G06F1/20 ,  H02G5/00 ,  H05K1/18

CPC分类号： H05K7/20927 ,  H01L23/473 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/0557 ,  H01L2224/29101 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/00 ,  H01L2224/05552

摘要： A reconfigurable high performance computer occupies less than 360 cubic inches and has an approximate compute power of 0.7 teraflops per second while consuming less than 1000 watts. The computer includes a novel stack of semiconductor substrate assemblies. Some semiconductor substrate assemblies involve field programmable gate array (FPGA) dice that are directly surface mounted, as bare die, to a semiconductor substrate. Other semiconductor substrate assemblies of the stack involve bare memory integrated circuit dice that are directly surface mounted to a semiconductor substrate. Elastomeric connectors interconnect adjacent semiconductor substrates proceeding down the stack. Tines of novel comb-shaped power bus bar assembly structures extend into the stack to supply DC supply voltages. The supply voltages are supplied from bus bars, through vias in the semiconductor substrates, and to the integrated circuits on the other side of the substrates. The power bus bars also serve as capacitors and guides for liquid coolant.

摘要翻译： 可重新配置的高性能计算机占用小于360立方英寸，并且具有每秒0.7 teraflops的近似计算能力，同时消耗少于1000瓦特。 该计算机包括一组新的半导体衬底组件。 一些半导体衬底组件涉及作为裸芯片直接表面安装到半导体衬底的现场可编程门阵列（FPGA）裸片。 堆叠的其他半导体衬底组件包括直接表面安装到半导体衬底的裸存储器集成电路裸片。 弹性连接器将相邻的半导体衬底互相连接，沿堆叠进入。 新颖的梳状电源母线组合结构的齿条延伸到堆叠中以提供直流电源电压。 电源电压由母线，半导体衬底中的通孔以及衬底另一侧的集成电路提供。 电力母线还用作液体冷却剂的电容器和导轨。

公开(公告)号：US20090079084A1

公开(公告)日：2009-03-26

申请号：US11975058

申请日：2007-10-16

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H05K7/20927 ,  H01L23/473 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/0557 ,  H01L2224/29101 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/00 ,  H01L2224/05552

摘要： An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigapascals (gPa) and the soft dielectric has a hardness of less than three gPa. The tube of soft dielectric and the metal conductor are both embedded within the volume of insulator. The tube defines a central volume and the metal conductor extends in a direction through the central volume for a distance of at least one inch. The metal conductor is encircled by the soft dielectric when the apparatus is viewed in a cross-sectional plane perpendicular to the direction. The metal conductor may include a plurality of bend portions. The metal conductor does not break when the apparatus is temperature cycled over a range from zero to eighty five degrees Celsius.

摘要翻译： 一种装置包括设置在半导体衬底的顶表面上的绝缘体体积，软电介质管和金属导体。 绝缘体的硬度大于约3吉帕斯卡（gPa），软电介质具有小于3gPa的硬度。 软电介质管和金属导体都嵌入在绝缘体的体积内。 管限定中心体积，并且金属导体沿着穿过中心体积的方向延伸至少一英寸的距离。 当在垂直于该方向的横截面中观察装置时，金属导体被软电介质环绕。 金属导体可以包括多个弯曲部分。 当设备在零度至摄氏度摄氏八十度的范围内温度循环时，金​​属导体不会断裂。

公开(公告)号：US07362121B1

公开(公告)日：2008-04-22

申请号：US10860237

申请日：2004-06-02

申请人： Robert O. Conn ,  Steven J. Carey ,  Siuki Chan ,  William H. Pabst

发明人： Robert O. Conn ,  Steven J. Carey ,  Siuki Chan ,  William H. Pabst

IPC分类号： G01R31/02

CPC分类号： G01R31/2875 ,  G01R31/287 ,  G01R31/31905

摘要： A system replicates the rapid temperature increases that are believed to cause microbump failures in certain applications of programmable logic devices (PLDs). The system configures a PLD under test with a circuit that switches a large amount of current and generates a large amount of heat when the circuit is clocked. The system monitors the temperature of the PLD and controls the switching of the circuit to achieve a predetermined temperature within a predetermined time period. The PLD is cooled, and the thermal cycling is repeated. The system detects microbump failures and communicates failure data to a computer for logging and analysis.

摘要翻译： 系统复制了在可编程逻辑器件（PLD）的某些应用中被认为导致微型块故障的快速升温。 该系统通过切换大量电流的电路来配置待测的PLD，并在电路被计时时产生大量的热量。 系统监视PLD的温度并控制电路的切换以在预定时间段内达到预定温度。 PLD被冷却，重复热循环。 系统检测微型计算机故障，并将故障数据传送到计算机进行记录和分析。

公开(公告)号：US07084487B1

公开(公告)日：2006-08-01

申请号：US10732494

申请日：2003-12-09

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： H01L23/552

CPC分类号： H01L24/73 ,  H01L23/34 ,  H01L23/552 ,  H01L24/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/91 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An integrated circuit die contains digital circuitry that emits noise (for example, in the audio frequency range) in the form of electromagnetic radiation. The integrated circuit die is provided with a shielded platform above the digital circuitry. The shielded platform has one metal plate that is coupled to an analog supply voltage source and another metal plate that is coupled to an analog ground terminal. The digital circuitry is coupled to a digital supply voltage source. A second die with noise-sensitive analog circuitry is stacked on the shielded platform and is shielded by the shielded platform from the noise. The analog circuitry is powered by the analog supply voltage source. Conductive vias in a predetermined pattern protrude through the shielded platform and provide a standardized way of connecting any one of numerous noise-sensitive second dice to the relatively noisy digital circuitry of the underlying die.

摘要翻译： 集成电路管芯包含以电磁辐射的形式发出噪声（例如在音频范围内）的数字电路。 集成电路管芯在数字电路之上设置有屏蔽平台。 屏蔽平台具有耦合到模拟电源电压源的一个金属板和耦合到模拟接地端子的另一金属板。 数字电路耦合到数字电源电压源。 具有噪声敏感的模拟电路的第二个芯片堆叠在屏蔽平台上，并被屏蔽平台屏蔽，免受噪音干扰。 模拟电路由模拟电源电压供电。 具有预定图案的导电孔通过屏蔽平台突出，并提供将多个噪声敏感的第二骰子中的任何一个连接到下面的芯片的相对嘈杂的数字电路的标准化方式。