公开(公告)号：US11482554B2

公开(公告)日：2022-10-25

申请号：US16898610

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang ,  Yungcheol Kong ,  Hyunsu Jun ,  Kyoungsei Choi

IPC: H01L27/146 ,  H01L31/0203 ,  H01L23/00 ,  H01L31/024

Abstract: A semiconductor package including a substrate, a memory chip on the substrate, a mold layer on the substrate to cover a side surface of the memory chip, an image sensor chip on the memory chip and the mold layer, and a connection terminal between and electrically connecting the memory chip to the image sensor chip may be provided.

公开(公告)号：US20220293566A1

公开(公告)日：2022-09-15

申请号：US17552614

申请日：2021-12-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Sick Park ,  Un-Byoung Kang ,  Jongho Lee ,  Teak-Hoon Lee

IPC: H01L25/065 ,  H01L23/00

Abstract: Disclosed is a semiconductor package with increased thermal radiation efficiency, which includes: a first die having signal and dummy regions and including first vias in the signal region, a second die on the first die and including second vias in the signal region, first die pads on a top surface of the first die and coupled to the first vias, first connection terminals on the first die pads which couple the second vias to the first vias, second die pads in the dummy region and on the top surface of the first die, and second connection terminals on the second die pads and electrically insulated from the first vias and the second vias. Each of the second die pads has a rectangular planar shape whose major axis is provided along a direction that leads away from the signal region.

公开(公告)号：US11302660B2

公开(公告)日：2022-04-12

申请号：US16803529

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Un-Byoung Kang ,  Jin Ho An ,  Jongho Lee ,  Jeonggi Jin ,  Atsushi Fujisaki

IPC: H01L23/00

Abstract: Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

公开(公告)号：US20170330767A1

公开(公告)日：2017-11-16

申请号：US15586716

申请日：2017-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Un-Byoung Kang ,  Tae-Je CHO ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC: H01L21/48 ,  C23C14/58 ,  C23C14/34 ,  C23C14/20 ,  C23C14/06 ,  C23C14/04 ,  C23C14/02 ,  B05D7/00 ,  B05D3/02 ,  B05D1/38 ,  B05D1/32 ,  B05D1/00

CPC classification number: H01L21/4857 ,  B05D1/005 ,  B05D1/32 ,  B05D1/38 ,  B05D3/0209 ,  B05D7/546 ,  C23C14/024 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/205 ,  C23C14/34 ,  C23C14/588 ,  C23C18/00 ,  C23C18/38 ,  H01L21/486 ,  H01L23/4334 ,  H01L23/473 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/18161 ,  H05K3/465 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/0588 ,  H01L2924/01047 ,  H01L2224/81

Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.

公开(公告)号：US09196505B2

公开(公告)日：2015-11-24

申请号：US13903164

申请日：2013-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang ,  Kwang-Chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/683 ,  H01L25/065 ,  H01L27/146 ,  H01L23/498

CPC classification number: H01L21/4835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/14618 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06138 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented.

Abstract translation: 在半导体器件中，有机绝缘图案设置在第一和第二重新布线图案之间。 有机绝缘图案可以吸收当第一和第二重新布线图案在加热下膨胀时发生的物理应力。 由于有机绝缘图案设置在第一和第二重新布线图案之间，所以可以相对于其中在重新布线图案之间设置半导体图案的半导体器件来增加绝缘性能。 此外，由于在第一和第二重新布线图案和有机绝缘图案之间以及基板和有机绝缘图案之间设置种子层图案，所以第一和第二布线图案的粘合强度提高。 这也减少了分层问题。 此外，种子层图案防止形成重新布线图案的金属扩散到有机绝缘图案。 因此，可以实现具有增强的可靠性的半导体器件。

公开(公告)号：US08852988B2

公开(公告)日：2014-10-07

申请号：US13909160

申请日：2013-06-04

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyung-Sun Jang ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

IPC: H01L31/18 ,  H01L27/146

CPC classification number: H01L31/18 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/13

Abstract: A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括具有第一表面，第二表面和像素区域的半导体芯片，设置在第一表面上的第一粘附图案，设置在第一粘附图案和像素区域之间并设置在第一表面上的第二粘合图案，以及 设置在第二表面上的外部连接端子，其中第二粘合图案和外部连接端子彼此重叠设置。