公开(公告)号：US08183662B2

公开(公告)日：2012-05-22

申请号：US13273546

申请日：2011-10-14

申请人： François Hébert ,  Kai Liu

发明人： François Hébert ,  Kai Liu

IPC分类号： H01L21/70 ,  H01L21/00

CPC分类号： H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099 ,  H01L2224/84

摘要： A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.

摘要翻译： 公开了具有集成旁路电容器的顶侧冷却紧凑型半导体封装。 顶侧冷却的紧凑型半导体封装包括具有端子引线的电路基板，接合在电路基板顶上的多个半导体管芯，用于将半导体管芯的顶部接触区域与电路基板接合和互连的许多仰角自适应互连板，第一构件 所述高度自适应互连板具有第一平顶区域，并且所述仰角自适应互连板的第二构件具有与所述第一平顶区域平齐的第二平顶区域，具有两个电容器端子的旁路电容器 位于其端部，并且通过第一平顶部区域和第二平顶部区域结合到两个互连板构件的顶部，以减少互连寄生阻抗。

公开(公告)号：US08168486B2

公开(公告)日：2012-05-01

申请号：US12823060

申请日：2010-06-24

申请人： François Hébert

发明人： François Hébert

IPC分类号： H01L29/778

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

摘要： Various embodiments of the disclosure include the formation of enhancement-mode (e-mode) gate injection high electron mobility transistors (HEMT). Embodiments can include GaN, AlGaN, and InAlN based HEMTs. Embodiments also can include self-aligned P-type gate and field plate structures. The gates can be self-aligned to the source and drain, which can allow for precise control over the gate-source and gate-drain spacing. Additional embodiments include the addition of a GaN cap structure, an AlGaN buffer layer, AlN, recess etching, and/or using a thin oxidized AlN layer. In manufacturing the HEMTs according to present teachings, selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) can both be utilized to form gates.

摘要翻译： 本公开的各种实施例包括形成增强型（e模式）栅极注入高电子迁移率晶体管（HEMT）。 实施例可以包括GaN，AlGaN和基于InAlN的HEMT。 实施例还可以包括自对准P型门和场板结构。 栅极可以与源极和漏极自对准，这可以精确控制栅极源极和栅极 - 漏极间隔。 另外的实施例包括添加GaN帽结构，AlGaN缓冲层，AlN，凹陷蚀刻和/或使用薄的氧化AlN层。 在根据本教导制造HEMT时，可以利用选择性外延生长（SEG）和外延横向过度生长（ELO）来形成栅极。

公开(公告)号：US08148256B2

公开(公告)日：2012-04-03

申请号：US12541881

申请日：2009-08-14

申请人： François Hébert ,  Anup Bhalla

发明人： François Hébert ,  Anup Bhalla

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/85201 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.

摘要翻译： 公开了一种铜键合兼容的键合焊盘结构及其相关方法。 器件接合焊盘结构包括由互连金属的区域和非导电钝化材料的区域形成的缓冲结构，该缓冲结构为器件的下层和结构提供缓冲。

公开(公告)号：US20110201174A1

公开(公告)日：2011-08-18

申请号：US13066373

申请日：2011-04-12

申请人： François Hébert ,  Tao Feng

发明人： François Hébert ,  Tao Feng

IPC分类号： H01L21/3115

CPC分类号： H01L29/7802 ,  H01L29/0653 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.

公开(公告)号：US07999363B2

公开(公告)日：2011-08-16

申请号：US11657862

申请日：2007-01-25

申请人： François Hébert ,  Ming Sun

发明人： François Hébert ,  Ming Sun

IPC分类号： H01L23/495

CPC分类号： H01L25/18 ,  H01L23/62 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A resetable over-current self-protecting semiconductor power device comprises a vertical power semiconductor chip and an over-current protection layer composed of current limiting material such as a PTC material. The over-current protection layer may be sandwiched between the vertical power semiconductor chip and a conductive plate, which could be a leadframe, a metal plate, a PCB plate or a PCB that the device is mounted on.

摘要翻译： 可复位的过流自保护半导体功率器件包括垂直功率半导体芯片和由诸如PTC材料的限流材料构成的过电流保护层。 过电流保护层可以夹在垂直功率半导体芯片和导电板之间，该导电板可以是装置安装在其上的引线框，金属板，PCB板或PCB。

公开(公告)号：US07939370B1

公开(公告)日：2011-05-10

申请号：US12608853

申请日：2009-10-29

申请人： Jun Lu ,  François Hébert

发明人： Jun Lu ,  François Hébert

IPC分类号： H01L21/00

CPC分类号： H01L23/492 ,  H01L24/36 ,  H01L24/40 ,  H01L25/071 ,  H01L25/072 ,  H01L25/16 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/37099

摘要： The present invention features a power semiconductor package and a method of forming the same that includes forming, in the body, a stress relief region disposed between a pair of mounting regions and attaching a semiconductor die in each of the mounting regions. The semiconductor die has first and second sets of electrical contacts with the first set being on a first surface of the semiconductor die and the second set being disposed upon a second surface of the semiconductor die opposite to the first surface. The first set is in electrical communication with the mounting region. Walls are formed on outer sides of the pair of mounting regions, defining a shaped body, with the shaped body and walls defining an electrically conductive path that extends from the first set and terminates on side of the package common with the second set.

摘要翻译： 本发明的特征在于功率半导体封装及其形成方法，其包括在主体中形成设置在一对安装区域之间的应力释放区域，并且在每个安装区域中安装半导体管芯。 半导体管芯具有第一组和第二组电触点，第一组在半导体管芯的第一表面上，第二组设置在与第一表面相对的半导体管芯的第二表面上。 第一组与安装区域电连通。 壁形成在一对安装区域的外侧，限定成形体，成形体和壁限定从第一组延伸并终止于与第二组共同的包装侧的导电路径。

公开(公告)号：US07893488B2

公开(公告)日：2011-02-22

申请号：US12321435

申请日：2009-01-21

申请人： François Hébert

发明人： François Hébert

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734

摘要： This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.

公开(公告)号：US07884452B2

公开(公告)日：2011-02-08

申请号：US11986673

申请日：2007-11-23

申请人： Tao Feng ,  Xiaotian Zhang ,  François Hébert

发明人： Tao Feng ,  Xiaotian Zhang ,  François Hébert

IPC分类号： H01L23/495 ,  H01F5/00

CPC分类号： H01L23/495 ,  H01F17/0033 ,  H01F2027/2814 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor power device package having a lead frame-based integrated inductor is disclosed. The semiconductor power device package includes a lead frame having a plurality of leads, a inductor core attached to the lead frame such that a plurality of lead ends are exposed through a window formed in the inductor core, a plurality of bonding wires, ones of the plurality of bonding wires coupling each of the plurality of lead ends to adjacent leads about the inductor core to form the inductor, and a power integrated circuit coupled to the inductor. In alternative embodiments, a top lead frame couples each of the plurality of lead ends to adjacent leads about the inductor core by means of a connection chip.

摘要翻译： 公开了一种具有引线框架的集成电感器的半导体功率器件封装。 半导体功率器件封装包括具有多个引线的引线框架，附接到引线框架的电感器芯，使得多个引线端通过形成在电感器芯中的窗体露出，多个接合线， 多个接合线将多个引线端中的每一个连接到围绕电感器芯的相邻引线以形成电感器，以及耦合到电感器的功率集成电路。 在替代实施例中，顶部引线框架通过连接芯片将多个引线端中的每一个耦合到围绕电感器芯的相邻引线。

公开(公告)号：US20110012701A1

公开(公告)日：2011-01-20

申请号：US12891105

申请日：2010-09-27

申请人： Jun Lu ,  François Hébert

发明人： Jun Lu ,  François Hébert

IPC分类号： H01F5/00 ,  H01F7/06

CPC分类号： H01F17/0013 ,  H01F27/29 ,  H01F41/046 ,  H01L2224/16235 ,  H01L2924/15311 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49073

摘要： A multilayer inductor is disclosed. The multilayer inductor includes a bottom magnetic layer having an external conductive pattern formed on a bottom surface thereof for connection to a substrate such as a printed circuit board. The bottom external conductive pattern includes signal/power contacts and first and second inductor electrodes. A top magnetic layer includes a top external conductive pattern having signal/power contacts and inductor electrode contacts. An inductor conductive pattern formed on the top surfaces of intermediate magnetic layers disposed between the top and bottom magnetic layers are electrically coupled to each other by means of through holes to form a spiral inductor element. The spiral inductor element is coupled to the first inductor electrode by means of a through hole formed in the bottom magnetic layer and to the second inductor electrode by means of power conductive traces formed on side surfaces of the multilayer inductor. Flux density reducing layers may be inserted directly above the bottom magnetic layer and directly below the top magnetic layer. Signal/power conductive traces formed on side surfaces of the multilayer inductor provide signal/power routing between the top magnetic layer signal/power contacts and the bottom magnetic layer signal/power contacts. The top external conductive pattern accommodates a semiconductor chip in a flip chip configuration.

摘要翻译： 公开了一种多层电感器。 多层电感器包括底部磁性层，其具有形成在其底表面上的外部导电图案，用于连接到诸如印刷电路板的基板。 底部外部导电图案包括信号/电源触点和第一和第二电感器电极。 顶部磁性层包括具有信号/功率触点和电感器电极触点的顶部外部导电图案。 形成在设置在顶部和底部磁性层之间的中间磁性层的顶表面上的电感器导电图案通过通孔彼此电耦合以形成螺旋形电感器元件。 螺旋电感器元件通过形成在底部磁性层中的通孔和形成在多层电感器的侧表面上的电力导电迹线耦合到第一电感器电极。 磁通密度降低层可以直接插入底部磁性层的正上方，并且直接位于顶部磁性层的正下方。 形成在多层电感器的侧表面上的信号/电力导电迹线提供顶层磁层信号/电源触点和底部磁层信号/电源触点之间的信号/功率布线。 顶部外部导电图案以倒装芯片配置容纳半导体芯片。

公开(公告)号：US07843303B2

公开(公告)日：2010-11-30

申请号：US12315703

申请日：2008-12-08

申请人： Jun Lu ,  François Hébert

发明人： Jun Lu ,  François Hébert

IPC分类号： H01F5/00 ,  H01F27/04 ,  H01F27/29 ,  H01F27/28 ,  H01F7/06

CPC分类号： H01F17/0013 ,  H01F27/29 ,  H01F41/046 ,  H01L2224/16235 ,  H01L2924/15311 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49073

摘要： A multilayer inductor is disclosed. The multilayer inductor includes a bottom magnetic layer having an external conductive pattern formed on a bottom surface thereof for connection to a substrate such as a printed circuit board. The bottom external conductive pattern includes signal/power contacts and first and second inductor electrodes. A top magnetic layer includes a top external conductive pattern having signal/power contacts and inductor electrode contacts. An inductor conductive pattern formed on the top surfaces of intermediate magnetic layers disposed between the top and bottom magnetic layers are electrically coupled to each other by means of through holes to form a spiral inductor element. The spiral inductor element is coupled to the first inductor electrode by means of a through hole formed in the bottom magnetic layer and to the second inductor electrode by means of power conductive traces formed on side surfaces of the multilayer inductor. Flux density reducing layers may be inserted directly above the bottom magnetic layer and directly below the top magnetic layer. Signal/power conductive traces formed on side surfaces of the multilayer inductor provide signal/power routing between the top magnetic layer signal/power contacts and the bottom magnetic layer signal/power contacts. The top external conductive pattern accommodates a semiconductor chip in a flip chip configuration.

摘要翻译： 公开了一种多层电感器。 多层电感器包括底部磁性层，其具有形成在其底表面上的外部导电图案，用于连接到诸如印刷电路板的基板。 底部外部导电图案包括信号/电源触点和第一和第二电感器电极。 顶部磁性层包括具有信号/功率触点和电感器电极触点的顶部外部导电图案。 形成在设置在顶部和底部磁性层之间的中间磁性层的顶表面上的电感器导电图案通过通孔彼此电耦合以形成螺旋形电感器元件。 螺旋电感器元件通过形成在底部磁性层中的通孔和形成在多层电感器的侧表面上的电力导电迹线耦合到第一电感器电极。 磁通密度降低层可以直接插入底部磁性层的正上方，并且直接位于顶部磁性层的正下方。 形成在多层电感器的侧表面上的信号/电力导电迹线提供顶层磁层信号/电源触点和底部磁层信号/电源触点之间的信号/功率布线。 顶部外部导电图案以倒装芯片配置容纳半导体芯片。