公开(公告)号：US09880952B2

公开(公告)日：2018-01-30

申请号：US14713061

申请日：2015-05-15

Applicant: Toshiba Memory Corporation

Inventor： Tetsuhiko Azuma

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1642 ,  G06F13/1673 ,  G06F13/4031 ,  G06F13/4282

Abstract: According to one embodiment, there is provided a bus access controller including a memory, multiple buffers, and an issuance circuit. Information necessary for bus access can be set in the memory. The multiple buffers store information set in the memory. The issuance circuit is connected to a bus. The issuance circuit issues a bus-access instruction, according to information stored in a buffer selected from among the multiple buffers in response to a request.

公开(公告)号：US09866540B2

公开(公告)日：2018-01-09

申请号：US15145052

申请日：2016-05-03

Applicant: Cavium, Inc.

Inventor： Gregg A. Bouchard ,  Rajan Goyal ,  Gregory E. Lund

IPC: G06F21/00 ,  H04L29/06 ,  G06F13/16 ,  G06F12/0802 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/00 ,  G06F3/06 ,  G06F11/20 ,  G06F12/126 ,  G06N5/02 ,  H04L12/26 ,  H04L12/747 ,  H04L12/851 ,  H04L12/801 ,  H04L12/741 ,  G06F9/50 ,  H04L29/08 ,  G06F9/46 ,  G11C7/10 ,  G06F12/0868

CPC classification number: H04L63/06 ,  G06F3/0629 ,  G06F3/0647 ,  G06F9/46 ,  G06F9/5016 ,  G06F9/5027 ,  G06F11/203 ,  G06F12/00 ,  G06F12/0207 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/0802 ,  G06F12/0868 ,  G06F12/126 ,  G06F13/16 ,  G06F13/1642 ,  G06N5/02 ,  G06N5/027 ,  G11C7/1075 ,  H04L43/18 ,  H04L45/742 ,  H04L45/745 ,  H04L47/2441 ,  H04L47/39 ,  H04L63/0227 ,  H04L63/0263 ,  H04L63/10 ,  H04L67/10 ,  H04L69/02 ,  H04L69/22 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/14 ,  Y02D10/22

Abstract: In one embodiment, a system includes a format block configured to receive a key, at least one rule, and rule formatting information. The rule can have one or more dimensions. The format block can be further configured to extract each of the dimensions from the at least one rule. The system can further include a plurality of dimension matching engines (DME). Each DME can be configured to receive the key and a corresponding formatted dimension, and process the key and the corresponding dimension for returning a match or nomatch. The system can further include a post processing block configured to analyze the matches or no matches returned from the DMEs and return a response based on the returned matches or nomatches.

公开(公告)号：US09846668B2

公开(公告)日：2017-12-19

申请号：US14730295

申请日：2015-06-04

Applicant: FUJITSU LIMITED

Inventor： Akiko Otoshi ,  Toshihisa Anbai

IPC: H05K7/10 ,  G06F13/40 ,  G06F13/16 ,  G06F13/364 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/4282

Abstract: The first buffers forward data from the first device to the respective corresponding second devices through the respective buses while the second buffers forward data from the respective corresponding second devices to the first device through the respective buses. In response to a simultaneous data transmission request to simultaneously transmit data from the first device to the second devices, the switch controller switches the first buffer into a data-forwarding enable state, and switches the second buffer into a data-forwarding disable state, for simultaneous data transmission from the first device to the plurality of the second devices. The pseudo-response generator generates pseudo-response signals acting as a plurality of response signals that the second devices transmit to the first device as a result of the simultaneous data transmission, and transmits the plurality of the pseudo-response signals to the first device. This configuration achieves simultaneous access to multiple devices.

公开(公告)号：US09830280B2

公开(公告)日：2017-11-28

申请号：US14746245

申请日：2015-06-22

Applicant: QUALCOMM TECHNOLOGIES International, Ltd.

Inventor： Klauss Riess ,  Victor Szeto ,  Gary Hum

IPC: G06F13/36 ,  G06F13/16 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F13/1642 ,  G06F13/385 ,  G06F13/4282

Abstract: A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input port, an SDIO data bus output port, and an SDIO bidirectional command port. Each SDIO unit has an address indicator within it associated with each SDIO unit. An SDIO unit will not respond to an SDIO command unless an SDIO unit address encoded in the SDIO command matches its address indicator. In some configurations, a single multiple SDIO (MSDIO) command may cause two or more SDIO units to return data to a host.

公开(公告)号：US20170339234A1

公开(公告)日：2017-11-23

申请号：US15162019

申请日：2016-05-23

Applicant: Wyse Technology L.L.C.

Inventor： Gokul Thiruchengode Vajravel

IPC: H04L29/08 ,  G06F13/16 ,  G06F9/455

CPC classification number: H04L67/141 ,  G06F9/45558 ,  G06F13/1642 ,  G06F2009/45579 ,  H04L67/145

Abstract: Session reliability can be improved when a USB device is redirected over a remote session. If a remote session is disconnected while a USB device is redirected over the remote session, a server-side agent and a client-side proxy will both receive a session disconnection notification. In response to this session disconnection notification, the agent and the proxy can each queue any I/O requests pertaining to a USB device that was being redirected over the now-disconnected remote session and commence waiting for a specified period of time. If the disconnected remote session is restored within the specified period of time, the agent and the proxy can send the queued I/O requests over the remote session. Otherwise, the agent and proxy can cause the queued I/O requests to be completed with the proper error status or discarded and can take appropriate steps to remove the device from the server and connect the device to the client.

公开(公告)号：US09824035B2

公开(公告)日：2017-11-21

申请号：US15426064

申请日：2017-02-07

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16 ,  G06F3/06 ,  G11C8/18

CPC classification number: G06F13/1673 ,  G06F1/10 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4027 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/20 ,  G11C8/12 ,  G11C8/18 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0407

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to receive command signals from the memory controller and to output module command signals and module control signals, and memory devices mounted on the module board to perform a first memory operation in response to the module command signals. The memory module further comprises a plurality of buffer circuits distributed across a surface of the module board. Each respective buffer circuit is associated with a respective set of the memory devices and includes logic that is configured to obtain timing information based on signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the data and strobe signals through the each respective buffer circuit in accordance with the timing information.

公开(公告)号：US09792231B1

公开(公告)日：2017-10-17

申请号：US14571183

申请日：2014-12-15

Applicant: Amazon Technologies, Inc.

Inventor： James Michael Thompson ,  Marc Stephen Olson ,  Jeevan Shankar ,  Danny Wei ,  John Robert Smiley ,  John Luther Guthrie, II ,  Nachiappan Arumugam ,  Benjamin Arthur Hawks

IPC: G06F13/16 ,  H04L29/08 ,  H04L12/26 ,  G06F9/50

CPC classification number: G06F13/1642 ,  G06F9/5061 ,  H04L43/028 ,  H04L67/10

Abstract: Systems and methods are described for dynamically detecting outliers in a set of input/output (I/O) metrics collected and aggregated by a storage volume network. An I/O request is received by a storage volume network, and an agent of the storage volume network associates primary and secondary identifiers with that I/O request. For example, a trace may be associated with a request to write data to a storage volume network, and spans may be associated with the individual operations required to fulfill that request. Once gathered, I/O metrics may be aggregated based on the associated identifiers. I/O metric information regarding outliers may be received from the storage volume network, processed, and published by an I/O metrics service to identify the outliers among the primary and secondary identifiers. These outliers may then be stored for further analysis, and may be utilized to determine improvements to the performance of a storage volume network.

公开(公告)号：US09779053B2

公开(公告)日：2017-10-03

申请号：US14580918

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Daniel S. Froelich ,  Venkatraman Iyer ,  Michelle C. Jen ,  Rahul R. Shah ,  Eric M. Lee

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4068 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/385 ,  G06F13/4282

Abstract: An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function as a drift buffer or an elastic buffer by a voltage level on a buffer control line. The physical interface also includes encoding logic that can be enabled or disabled by a voltage level on a logic control line. Further, the physical interface also includes and an ordered set generator that can be enabled or disabled by a voltage level on a communications control line.

公开(公告)号：US09772958B2

公开(公告)日：2017-09-26

申请号：US13285973

申请日：2011-10-31

Applicant: Jeffrey Clifford Mogul ,  Jayaram Mudigonda

Inventor： Jeffrey Clifford Mogul ,  Jayaram Mudigonda

IPC: H04L12/801 ,  G06F13/16

CPC classification number: G06F13/1642 ,  H04L47/10 ,  H04L47/12

Abstract: Example methods, apparatus, and articles of manufacture to control generation of memory access requests in processor systems are disclosed. A disclosed example method involves determining at a memory controller whether a memory access queue depth for a memory reference is greater than a first threshold. When the memory access queue depth for the memory reference is greater than the first threshold, an indication is sent to control generation of memory access requests corresponding to the memory reference.

公开(公告)号：US20170255587A1

公开(公告)日：2017-09-07

申请号：US15600335

申请日：2017-05-19

Applicant: INTEL CORPORATION

Inventor： John I. GARNEY ,  John S. HOWARD

IPC: G06F13/42 ,  H04L12/40 ,  G06F3/14 ,  G06F13/40 ,  H04N5/225

CPC classification number: G06F13/42 ,  G06F3/14 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/405 ,  G06F13/426 ,  G06F2213/0054 ,  G06F2213/40 ,  G06F2213/4002 ,  H04L12/40058 ,  H04L12/40123 ,  H04N5/225

Abstract: A method of and apparatus for communicating between a host and an agent. The method includes the step of performing a first transaction between a host controller and a hub. The hub is operable to perform a single transaction with an agent based on the first transaction. The method then includes the step of performing a second transaction between the host controller and the hub. The second transaction is based on the single transaction.