公开(公告)号：US11735242B2

公开(公告)日：2023-08-22

申请号：US17450852

申请日：2021-10-14

Applicant: Regents of the University of Minnesota

Inventor： Jian-Ping Wang ,  Delin Zhang ,  Protyush Sahu

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/18 ,  H10B61/00 ,  H10N50/85 ,  H10N52/00 ,  H10N52/80

CPC classification number: G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H10B61/00 ,  H10N50/85 ,  H10N52/00 ,  H10N52/80

Abstract: A magnetic device includes a layer stack comprising a first ferromagnetic layer; a spacer layer on the first ferromagnetic layer; a second ferromagnetic layer on the spacer layer; a dielectric barrier layer on the second ferromagnetic layer; an insertion layer positioned between the second ferromagnetic layer and the dielectric barrier layer; and a fixed layer or an electrode on the dielectric barrier layer. In some examples, a magnetic orientation of the second ferromagnetic layer is switched by a bias voltage across the layer stack without application of an external magnetic field; an antiferromagnetic coupling of the first and second ferromagnetic layers is increased by the bias voltage applying a negative charge to the fixed layer or the electrode, and the antiferromagnetic coupling of the first and second ferromagnetic layers is decreased by the bias voltage applying a positive charge to the fixed layer or the electrode.

公开(公告)号：US11683939B2

公开(公告)日：2023-06-20

申请号：US16396451

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Benjamin Buford ,  Angeline Smith ,  Noriyuki Sato ,  Tanay Gosavi ,  Kaan Oguz ,  Christopher Wiegand ,  Kevin O'Brien ,  Tofizur Rahman ,  Gary Allen ,  Sasikanth Manipatruni ,  Emily Walker

IPC: H10B61/00 ,  H10N50/10 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10B61/22 ,  H10N50/10 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80

Abstract: A memory apparatus includes a first electrode having a spin orbit material. The memory apparatus further includes a first memory device on a portion of the first electrode and a first dielectric adjacent to a sidewall of the first memory device. The memory apparatus further includes a second memory device on a portion of the first electrode and a second dielectric adjacent to a sidewall of the second memory device. A second electrode is on and in contact with a portion of the first electrode, where the second electrode is between the first memory device and the second memory device. The second electrode has a lower electrical resistance than an electrical resistance of the first electrode. The memory apparatus further includes a first interconnect structure and a second interconnect, each coupled with the first electrode.

公开(公告)号：US20240365684A1

公开(公告)日：2024-10-31

申请号：US18771471

申请日：2024-07-12

Applicant: TDK CORPORATION

Inventor： Tomoyuki SASAKI

IPC: H10N52/00 ,  G01R33/09 ,  G11B5/39 ,  G11C11/16 ,  G11C11/18 ,  H01F10/32 ,  H01L27/105 ,  H01L29/82 ,  H03B15/00 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10N52/00 ,  G01R33/098 ,  G11B5/39 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/18 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/329 ,  H01L27/105 ,  H01L29/82 ,  H03B15/00 ,  H03B15/006 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80 ,  H01F10/3286

Abstract: This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.

公开(公告)号：US12106791B2

公开(公告)日：2024-10-01

申请号：US17854785

申请日：2022-06-30

Applicant: Western Digital Technologies, Inc.

Inventor： Quang Le ,  Brian R. York ,  Cherngye Hwang ,  Xiaoyong Liu ,  Michael A. Gribelyuk ,  Xiaoyu Xu ,  Susumu Okamura ,  Kuok San Ho ,  Hisashi Takano ,  Randy G. Simmons

IPC: G11C11/16 ,  G11B5/39 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85 ,  H10N52/00 ,  H10N52/80

CPC classification number: G11C11/161 ,  G11B5/3906 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85 ,  H10N52/00 ,  H10N52/80

Abstract: The present disclosure generally relates to spin-orbit torque (SOT) devices comprising a bismuth antimony (BiSb) layer. The SOT devices further comprise one or more GeXNiFe layers, where at least one GeXNiFe layer is disposed in contact with the BiSb layer. The GeXNiFe layer has a thickness less than or equal to about 15 Å when used as an interlayer on top of the BiSb layer or less than or equal to 40 Å when used as a buffer layer underneath the BiSb. When the BiSb layer is doped with a dopant comprising a gas, a metal, a non-metal, or a ceramic material, the GeXNiFe layer promotes the BiSb layer to have a (012) orientation. When the BiSb layer is undoped, the GeXNiFe layer promotes the BiSb layer to have a (001) orientation. Utilizing the GeXNiFe layer allows the crystal orientation of the BiSb layer to be selected.

公开(公告)号：US12068746B2

公开(公告)日：2024-08-20

申请号：US17773945

申请日：2020-11-02

Applicant: Nanyang Technological University

Inventor： Chu Keong Gerard Joseph Lim ,  Chandrasekhar Murapaka ,  Wen Siang Lew

IPC: G11C11/16 ,  G11C11/18 ,  H03K19/18 ,  H03K19/21 ,  H10N52/00

CPC classification number: H03K19/18 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H03K19/21 ,  H10N52/00

Abstract: A magnetic logic device having two magnetic elements and a conductive element coupled to the two magnetic elements and arranged at least substantially perpendicular to the magnetic elements, wherein the device is configured, for each magnetic element, to have a magnetisation state with a perpendicular easy axis, and to switch the magnetisation state in response to a spin current generated in the magnetic element in response to a write current applied to the magnetic element, and configured to generate, as an output, a Hall voltage across the conductive element in response to a respective read current applied to each magnetic element, wherein a magnitude of the Hall voltage is variable, depending on a direction of the magnetisation state of each magnetic element and a direction of the respective read current applied to each magnetic element, for the device to provide outputs corresponding to one of a plurality of logical operations.

公开(公告)号：US12052934B2

公开(公告)日：2024-07-30

申请号：US17668514

申请日：2022-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Wei-Jen Chen ,  Ya-Jui Tsou ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Chih-Lin Wang

IPC: H10N52/80 ,  H10B61/00 ,  H10N52/00 ,  H10N52/01

CPC classification number: H10N52/80 ,  H10B61/00 ,  H10N52/00 ,  H10N52/01

Abstract: A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.

公开(公告)号：US12048251B2

公开(公告)日：2024-07-23

申请号：US17345084

申请日：2021-06-11

Applicant: TDK CORPORATION

Inventor： Tomoyuki Sasaki ,  Yohei Shiokawa ,  Eiji Komura ,  Keita Suda

IPC: H01L43/08 ,  G11C11/16 ,  G11C11/18 ,  H01L43/04 ,  H10N50/10 ,  H10N50/85 ,  H10N52/00 ,  H01F10/32 ,  H10N52/80

CPC classification number: H10N50/85 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  H10N50/10 ,  H10N52/00 ,  H01F10/3254 ,  H10N52/80

Abstract: Provided is a magnetoresistance effect element that suppresses re-adhesion of impurities during preparation and allows a write current to easily flow. The magnetoresistance effect element includes a first ferromagnetic layer, a second ferromagnetic layer; and a nonmagnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer. In the magnetoresistance effect element, the nonmagnetic layer is a tunnel barrier layer constituted by an insulator, a side surface of the first ferromagnetic layer, a side surface of the second ferromagnetic layer and a side surface of the nonmagnetic layer form a continuous inclined surface in any side surface, and a thickness of inside the nonmagnetic layer is thicker than a thickness of outside the nonmagnetic layer.

公开(公告)号：US12016251B2

公开(公告)日：2024-06-18

申请号：US17445831

申请日：2021-08-25

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Alexander Reznicek ,  Bahman Hekmatshoartabari ,  Ruilong Xie

IPC: H10N52/80 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01

CPC classification number: H10N52/80 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/329 ,  H10B61/20 ,  H10N50/01 ,  H10N50/10 ,  H10N52/00 ,  H10N52/01 ,  G11C11/1673 ,  H10N50/85

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a spin transfer torque (STT) magnetoresistive random access memory (MRAM) stack. The semiconductor structure may also include a spin orbit torque (SOT) MRAM stack vertically in series with the STT-MRAM. The SOT-MRAM stack may include a heavy metal spin hall effect rail configured to flip an SOT free-layer magnetic orientation in response to a horizontal signal through the heavy metal rail.

公开(公告)号：US11990899B2

公开(公告)日：2024-05-21

申请号：US17152552

申请日：2021-01-19

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Patrick Morrow ,  Anurag Chaudhry

IPC: H03K19/173 ,  H03K19/00 ,  H03K19/18 ,  H10N50/85 ,  H10N52/00 ,  H10N52/80

CPC classification number: H03K19/0002 ,  H03K19/18 ,  H10N50/85 ,  H10N52/00 ,  H10N52/80

Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

公开(公告)号：US11968911B2

公开(公告)日：2024-04-23

申请号：US17518571

申请日：2021-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin

IPC: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

CPC classification number: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ stack; forming a first hard mask on the first SOT layer; and using a second hard mask to pattern the first hard mask, the first SOT layer, and the MTJ stack to form a MTJ.