公开(公告)号：US11836385B2

公开(公告)日：2023-12-05

申请号：US17835809

申请日：2022-06-08

申请人： fmad engineering kabushiki gaisha

发明人： Aaron Foo

IPC分类号： G06F3/06 ,  G06F13/28 ,  G06F16/182 ,  G11C29/52 ,  G06F11/10

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0604 ,  G06F3/067 ,  G06F3/0631 ,  G06F3/0643 ,  G06F11/1068 ,  G06F13/287 ,  G06F16/182 ,  G11C29/52

摘要： An embodiment may involve a network interface configured to capture data packets into a binary format and a non-volatile memory configured to temporarily store the data packets received by way of the network interface. The embodiment may also involve a first array of processing elements each configured to independently and asynchronously: (i) read a chunk of data packets from the non-volatile memory, (ii) identify flows of data packets within the chunk, and (iii) generate flow representations for the flows. The embodiment may also involve a second array of processing elements configured to: (i) receive the flow representations from the first array of processing elements, (ii) identify and aggregate common flows across the flow representations into an aggregated flow representation, (iii) based on a filter specification, remove one or more of the flows from the aggregated flow representation, and (iv) write information from the aggregated flow representation to the database.

公开(公告)号：US20230352113A1

公开(公告)日：2023-11-02

申请号：US17636895

申请日：2021-08-04

申请人： UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

发明人： Jongeun LEE ,  Sugil LEE

IPC分类号： G11C29/52 ,  G06F17/16 ,  G06N3/04

CPC分类号： G11C29/52 ,  G06F17/16 ,  G06N3/04

摘要： The present disclosure provides a calculation error correction device including a first learning unit that trains an effective weight value prediction model for outputting an effective weight value matrix by using learning data in response to an input of the random weight value matrix, an effective weight value calculation unit that inputs a first weight value matrix into the effective weight value prediction model to derive the effective weight value matrix, a second learning unit that applies a second input vector to a target neural network as an input value, applied the effective weight value matrix as a weight value, and trains the weight value such that an output vector follows a result of multiplication of the second input vector and the first weight value matrix, and a control unit that performs matrix-vector multiplication by mapping the first input vector and the trained weight value matrix to the resistive memory.

公开(公告)号：US20230342039A1

公开(公告)日：2023-10-26

申请号：US18336188

申请日：2023-06-16

申请人： KIOXIA CORPORATION

发明人： Daisuke HASHIMOTO

IPC分类号： G06F3/06 ,  G06F11/34 ,  G06F11/14 ,  G06F11/07 ,  G06F9/4401 ,  G06F11/00 ,  G06F11/10 ,  G06F12/10 ,  G11C29/52

CPC分类号： G06F3/0616 ,  G06F11/3485 ,  G06F11/1417 ,  G06F11/1456 ,  G06F11/0754 ,  G06F9/4401 ,  G06F11/004 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/10 ,  G11C29/52 ,  G06F9/4416 ,  G06F9/4403 ,  G06F9/4406 ,  G06F11/1461 ,  G06F11/3419 ,  G06F2201/81 ,  G06F9/44505

摘要： According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader. The host device is configured to determine whether a first condition is established based on information obtained from the nonvolatile memory device; and rewrite, when determined the first condition is established, the bootloader so that an emergency software is initiated when booting the host device. The emergency software is executed on the host device. The host device is capable of issuing only a read command to the nonvolatile memory device under a control of the emergency software.

公开(公告)号：US11799496B2

公开(公告)日：2023-10-24

申请号：US17726349

申请日：2022-04-21

申请人： Micron Technology, Inc.

发明人： Jongtae Kwak

IPC分类号： G06F7/02 ,  H03M13/11 ,  G11C29/52 ,  G06F11/10

CPC分类号： H03M13/1108 ,  G06F11/1068 ,  G11C29/52

摘要： Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).

公开(公告)号：US11797383B2

公开(公告)日：2023-10-24

申请号：US17167254

申请日：2021-02-04

申请人： Micron Technology, Inc.

发明人： Jung Sheng Hoei ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Kishore K. Muchherla ,  Sivagnanam Parthasarathy ,  Peter Feeley

IPC分类号： G06F11/10 ,  G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C29/00 ,  H10B43/27 ,  G11C29/52

CPC分类号： G06F11/1072 ,  G06F3/064 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0688 ,  G06F11/10 ,  G06F11/1076 ,  G11C11/5642 ,  G11C29/52 ,  G11C29/74 ,  H10B43/27 ,  G11C16/0483 ,  Y02D10/00

摘要： The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.

公开(公告)号：US20230335214A1

公开(公告)日：2023-10-19

申请号：US18295013

申请日：2023-04-03

申请人： Winbond Electronics Corp.

发明人： Liang-Hsiang CHIU

IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C29/52

CPC分类号： G11C29/52 ,  G11C5/14 ,  G11C7/1039

摘要： A peripheral circuit of a memory device includes a compensation circuit, a determination circuit, and a plurality of page buffers. The compensation circuit defines a leakage current. The determination circuit is coupled to the compensation circuit, and is operated according to the leakage current. The determination circuit includes a current source, a first current mirror, a second current mirror, a potentially-qualified-bit quantity control unit, a determination circuit enable control unit, a hysteresis circuit, and a first logic unit. The page buffers include an unselected page buffer and a selected page buffer. The unselected page buffer is coupled to the compensation circuit. The selected page buffer is coupled to the determination circuit.

公开(公告)号：US20230335175A1

公开(公告)日：2023-10-19

申请号：US17899785

申请日：2022-08-31

申请人： SK hynix Inc.

发明人： Woongrae KIM ,  Yoonna OH ,  Chul Moon JUNG

IPC分类号： G11C11/406 ,  G11C29/52 ,  G11C29/00

CPC分类号： G11C11/40615 ,  G11C11/40618 ,  G11C29/52 ,  G11C29/785

摘要： A method for operating a memory includes: receiving an active command and a row address; confirming that a portion of columns of a first row corresponding to the row address is replaced with a portion of columns of a second row; activating the first row and the second row; confirming activation of a random pulse; randomly selecting one among the row address corresponding to the first row and a row address corresponding to the second row in response to the activation of the random pulse; and sampling the selected row address as a sampling address.

公开(公告)号：US20230317200A1

公开(公告)日：2023-10-05

申请号：US18148357

申请日：2022-12-29

申请人： SK Hynix Inc. ,  Industry-Academic Cooperation Foundation Yonsei University

发明人： Giseok KIM ,  Jiyoung Kim ,  Wonjoon Jo ,  Sungho Park ,  Seongook Jung ,  Juhyun Park ,  Seung Ho Lee ,  Jungchan Lee

IPC分类号： G11C29/52 ,  G11C11/419

CPC分类号： G11C29/52 ,  G11C11/419

摘要： An error handling device includes a cross-voltage sense amplifier and an error handling circuit. The cross-voltage sense amplifier is configured to perform a normal sense operation and a cross sense operation. The normal sense operation generates normal sense data by providing an input voltage and a comparison voltage to first and second inputs of a comparator, respectively. The cross sense operation generates cross sense data by providing the input voltage and the comparison voltage to the second and first inputs of the comparator, respectively. The error handling circuit identifies a location of an error using the normal sense data and the cross sense data and corrects the error.

公开(公告)号：US11769832B2

公开(公告)日：2023-09-26

申请号：US17963024

申请日：2022-10-10

申请人： Zeno Semiconductor, Inc.

发明人： Jin-Woo Han ,  Dinesh Maheshwari ,  Yuniarto Widjaja

IPC分类号： H01L29/78 ,  H01L27/12 ,  H10B12/00 ,  G11C29/12 ,  G11C11/408 ,  G11C11/4096 ,  G06F11/10 ,  G11C29/52 ,  G11C7/02

CPC分类号： H01L29/7841 ,  H01L27/1211 ,  H10B12/20 ,  G06F11/1068 ,  G11C7/02 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/12 ,  G11C29/52 ,  H01L29/785

摘要： A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

公开(公告)号：US11768732B2

公开(公告)日：2023-09-26

申请号：US17530748

申请日：2021-11-19

申请人： KIOXIA CORPORATION

发明人： Yuta Kumano ,  Hironori Uchikawa ,  Kosuke Morinaga ,  Naoaki Kokubun ,  Masahiro Kiyooka ,  Yoshiki Notani ,  Kenji Sakurada ,  Daiki Watanabe

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C11/56 ,  H03M13/00 ,  H03M13/37 ,  G11C29/52 ,  H03M13/11 ,  G11C29/04 ,  G11C16/26 ,  G11C29/42

CPC分类号： G06F11/1048 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1068 ,  G11C11/5642 ,  G11C29/52 ,  H03M13/3715 ,  H03M13/3746 ,  H03M13/6325 ,  G11C16/26 ,  G11C29/42 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/1108 ,  H03M13/1111

摘要： According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.