公开(公告)号：US09871034B1

公开(公告)日：2018-01-16

申请号：US13731108

申请日：2012-12-30

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L29/80 ,  H01L27/04 ,  H01L27/088

CPC classification number: H01L27/04 ,  H01L27/088

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; and a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, and the second layer overlying the at least one metal layer; wherein the material composition of at least one of the plurality of second single crystal transistors is substantially different than the material composition of at least one of the plurality of first transistors.

公开(公告)号：US20170301667A1

公开(公告)日：2017-10-19

申请号：US15482761

申请日：2017-04-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L27/06 ,  H01L23/34 ,  H03K19/096 ,  H01L23/48 ,  H01L23/50 ,  H01L23/525

CPC classification number: H01L27/0688 ,  G01R31/3187 ,  G01R31/31937 ,  G11C11/401 ,  G11C29/006 ,  G11C29/76 ,  H01L22/22 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5252 ,  H01L23/5286 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H03K3/0375 ,  H03K19/096 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1776 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/29099

Abstract: A 3D structure, the structure including: a first stratum overlaid by a second stratum, the second stratum is less than two microns thick, where the first stratum includes an array of memory cells including at least four rows of memory cells, each of the rows is controlled by a bit-line, where the array of memory cells includes a plurality of columns of memory cells, each of the columns is controlled by a word-line, and where the second stratum includes memory control circuits directly connected to the bit-lines and the word-lines.

公开(公告)号：US20170162585A1

公开(公告)日：2017-06-08

申请号：US15222832

申请日：2016-07-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L27/112 ,  H01L23/525

CPC classification number: H01L27/1128 ,  G06F17/505 ,  G06F17/5068 ,  H01L21/768 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/1305 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A 3D semiconductor device including: a first layer including a first monocrystalline layer, the first layer including first logic cells; a second layer including a monocrystalline semiconductor layer, the second layer overlying the first layer, the second layer including second transistors, where the logic cells include a Look-Up-Table logic cell, and where the second transistors are aligned to the first logic cells with less than 200 nm alignment error.

公开(公告)号：US20170117291A1

公开(公告)日：2017-04-27

申请号：US15333138

申请日：2016-10-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/115 ,  H01L27/02 ,  H01L29/167 ,  H01L23/528 ,  H01L29/47 ,  H01L29/78

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11514 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/167 ,  H01L29/47 ,  H01L29/7827 ,  H01L29/792

Abstract: A multilevel semiconductor device, including: a first level including a first array of first memory cells; a second level including a second array of second memory cells, the first level is overlaid by the second level, where at least one of the first memory cells includes a vertically oriented first transistor, and where at least one of the second memory cells includes a vertically oriented second transistor, and where the first transistor includes a first single crystal channel, and where the second transistor includes a second single crystal channel, and where the first transistor is self-aligned to the second transistor.

公开(公告)号：US09613887B2

公开(公告)日：2017-04-04

申请号：US15079017

申请日：2016-03-23

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L23/48 ,  H01L27/088 ,  H01L23/367 ,  H01L23/522 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.

公开(公告)号：US09564432B2

公开(公告)日：2017-02-07

申请号：US14509288

申请日：2014-10-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L27/088 ,  G11C17/14 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L23/525 ,  H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/118 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/177 ,  H01L21/8226 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L27/088 ,  G11C17/14 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8226 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/177 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; where the second layer includes at least one through layer via to provide connection between at least one of the second transistors and at least one of the first transistors, where the at least one through layer via has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; and a second set of external connections overlying the second layer to connect the device to external devices.

Abstract translation: 一种半导体器件，包括：第一层，包括单晶材料和第一晶体管，所述第一晶体管由第一隔离层覆盖; 包括第二晶体管并覆盖第一隔离层的第二层，第二晶体管包括单晶材料; 其中所述第二层包括至少一个贯通层通孔，以在所述第二晶体管中的至少一个与所述第一晶体管中的至少一个之间提供连接，其中所述至少一个贯通层通孔的直径小于200nm; 第一层的第一组外部连接，用于将设备连接到外部设备; 以及覆盖第二层以将设备连接到外部设备的第二组外部连接。

公开(公告)号：US09385058B1

公开(公告)日：2016-07-05

申请号：US13803437

申请日：2013-03-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/70 ,  H01L27/12 ,  H01L23/34

CPC classification number: H01L21/4871 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including first electronic circuits and a plurality of first single crystal transistors; at least one metal layer; and a second layer including second electronic circuits and a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; the second layer includes a through layer via with a diameter of less than 150 nm; a portion of the first electronic circuits is circumscribed by a first dice lane, and there are no conductive connections to the portion of the first electronic circuits that cross the first dice lane; wherein a portion of the second electronic circuits is circumscribed by a second dice lane, and there are no conductive connections to the portion of the second electronic circuits that cross the second dice lane, and the second dice lane is overlaying and aligned to the first dice lane.

Abstract translation: 一种集成电路装置，包括：基底晶片，包括第一电子电路和多个第一单晶晶体管; 至少一个金属层; 以及包括第二电子电路和多个第二单晶体晶体管的第二层，所述第二层覆盖所述至少一个金属层; 第二层包括直径小于150nm的贯通层通孔; 第一电子电路的一部分由第一骰子通道限定，并且不与第一电子电路的穿过第一骰子通道的部分的导电连接; 其中所述第二电子电路的一部分由第二骰子通道限定，并且没有与所述第二电子电路的穿过所述第二骰子通道的所述部分的导电连接，并且所述第二骰子通道覆盖并对齐到所述第一骰子 车道。

公开(公告)号：US20150340316A1

公开(公告)日：2015-11-26

申请号：US14814865

申请日：2015-07-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/528 ,  H01L27/108 ,  H01L27/115 ,  H01L27/24

CPC classification number: H01L23/528 ,  G11C5/025 ,  G11C5/04 ,  G11C8/16 ,  G11C11/403 ,  G11C13/0007 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/0688 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/2436 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/141 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2224/16145 ,  H01L2224/32145

Abstract: A 3D device, including: a first layer including a first memory including a first transistor; and a second layer including a second memory including a second transistor; where the second transistor is self-aligned to the first transistor, and where the first transistor and the second transistor each being a junction-less transistor.

Abstract translation: 一种3D设备，包括：包括第一存储器的第一层，所述第一存储器包括第一晶体管; 以及包括包括第二晶体管的第二存储器的第二层; 其中所述第二晶体管与所述第一晶体管自对准，并且其中所述第一晶体管和所述第二晶体管均为无结型晶体管。

公开(公告)号：US20150311142A1

公开(公告)日：2015-10-29

申请号：US14747599

申请日：2015-06-23

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/48 ,  H01L27/088 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D device including: a first layer including first transistors, the first layer overlaid by at least one interconnection layer; a second layer including second transistors, the second layer overlaying the interconnection layer; a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, where the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to a top or bottom surface of the 3D device.

Abstract translation: 一种3D设备，包括：包括第一晶体管的第一层，由至少一个互连层覆盖的第一层; 第二层，包括第二晶体管，第二层覆盖互连层; 将所述第二晶体管与所述互连层连接的多个电连接; 以及至少一个导热和非导电接触，其中所述至少一个导热和非导电接触将所述第二层热连接到所述3D器件的顶表面或底表面。

公开(公告)号：US09142553B2

公开(公告)日：2015-09-22

申请号：US14628231

申请日：2015-02-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H03K19/00 ,  H01L27/06 ,  H03K19/096 ,  H01L23/34 ,  H01L23/48 ,  H01L23/50

CPC classification number: H01L27/0688 ,  H01L23/34 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5252 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15311 ,  H03K19/096 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure and a second clock origin, where the second clock origin is connected to the first clock distribution structure with a plurality of through layer vias, and where the second layer thickness is less than 1 micrometer.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 包括第二晶体管的第二层，覆盖第一层互连层的第二晶体管，其中第一层包括第一时钟分布结构，其中第二层包括第二时钟分布结构和第二时钟源，其中第二时钟源为 连接到具有多个通过层通孔的第一时钟分配结构，并且其中第二层厚度小于1微米。