公开(公告)号：US20150255705A1

公开(公告)日：2015-09-10

申请号：US14634454

申请日：2015-02-27

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Emilie Trioux ,  Pascal Ancey ,  Stephane Monfray ,  Thomas Skotnicki ,  Skandar Basrour ,  Paul Muralt

IPC: H01L41/27 ,  C23C4/10 ,  C23C4/12 ,  H01L41/08 ,  F03G7/06

CPC classification number: H01L41/27 ,  B32B15/01 ,  C22F1/00 ,  C23C4/10 ,  C23C4/134 ,  C23C10/12 ,  F03G7/06 ,  H01L41/0805 ,  H01L41/0815 ,  H01L41/33 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49124

Abstract: A method of manufacturing bistable strips having different curvatures, each strip including a plurality of portion of layers of materials, wherein at least one specific layer portion is deposited by a plasma spraying method in conditions different for each of the strips.

Abstract translation: 制造具有不同曲率的双稳态条带的方法，每条条带包括多个材料层，其中至少一个特定层部分通过等离子体喷涂方法在对每个条带不同的条件下进行沉积。

公开(公告)号：US09087872B2

公开(公告)日：2015-07-21

申请号：US14168167

申请日：2014-01-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Favennec ,  Arnaud Tournier ,  François Roy

IPC: H01L21/762 ,  H01L27/146

CPC classification number: H01L21/76224 ,  H01L21/76237 ,  H01L27/1463

Abstract: A structure comprising at least one DTI-type insulating trench in a substrate, the trench being at the periphery of at least one active area of the substrate forming a pixel, the insulating trench including a cavity filled with a dielectric material, the internal walls of the cavity being covered with a layer made of a boron-doped material.

Abstract translation: 一种结构，其包括在衬底中的至少一个DTI型绝缘沟槽，所述沟槽位于形成像素的衬底的至少一个有源区域的外围，所述绝缘沟槽包括填充有电介质材料的腔体， 该腔被由硼掺杂材料制成的层覆盖。

公开(公告)号：US09075947B2

公开(公告)日：2015-07-07

申请号：US13911224

申请日：2013-06-06

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Manoj Kumar ,  Jean Guillorit ,  Navin Kumar Dayani

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: An input/output circuit layout has a first section in which first transistors having a thicker gate oxide are located and a second section in which second transistors having a thinner gate oxide are located. Due to process technology constraints, the gates of all of the second transistors are oriented in a single common direction. The second section has a perimeter having a square shape including a first edge and a second edge adjacent to the first edge. First connection pins coupled to the second transistors are provided with an orientation that extends inwardly from and perpendicular to the first edge. Second connection pins coupled to the second transistors are provided with an orientation that extends inwardly from and perpendicular to said second edge. The square shape and presence of pins on adjacent first and second edges permits rotation of the second section to fit within different orientations of the layout.

Abstract translation: 输入/输出电路布局具有第一部分，其中具有较厚栅极氧化物的第一晶体管位于其中，第二部分中具有较薄栅极氧化物的第二晶体管位于其中。 由于工艺技术的限制，所有第二晶体管的栅极定向在单一的共同方向。 第二部分具有包括与第一边缘相邻的第一边缘和第二边缘的正方形形状的周边。 耦合到第二晶体管的第一连接引脚具有从第一边缘向内并垂直于第一边缘延伸的取向。 耦合到第二晶体管的第二连接引脚具有从所述第二边缘向内并垂直于所述第二边缘延伸的取向。 在相邻的第一和第二边缘上的方形形状和销的存在允许第二部分的旋转以适应布局的不同取向。

公开(公告)号：US20150137242A1

公开(公告)日：2015-05-21

申请号：US14605064

申请日：2015-01-26

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： DAVID BARGE ,  PIERRE MORIN

IPC: H01L29/06 ,  H01L27/12

CPC classification number: H01L29/0653 ,  H01L21/76283 ,  H01L27/1203

Abstract: An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.

Abstract translation: 一个绝缘壁，分离形成在半导体层上的薄的半导体层中的晶体管，该绝缘层位于半导体衬底上的绝缘层上，该壁由绝缘材料形成，并且包括与薄层交叉的壁和绝缘层并穿透到衬底中 在绝缘层下方的衬底中延伸的延伸部。

公开(公告)号：US09018729B2

公开(公告)日：2015-04-28

申请号：US13895715

申请日：2013-05-16

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Raul Andres Bianchi ,  Pascal Fonteneau

IPC: H01L23/58 ,  H01L31/0256 ,  H01L27/144 ,  H01L31/18 ,  H01L29/66 ,  H01L29/866 ,  H01L29/06

CPC classification number: H01L31/0256 ,  H01L27/144 ,  H01L29/0684 ,  H01L29/66113 ,  H01L29/866 ,  H01L31/1892

Abstract: An avalance diode including, between two heavily-doped regions of opposite conductivity types arranged at the surface of a semiconductor region, a lightly-doped region, with length L of the lightly-doped region between the heavily-doped regions approximately ranging between 50 and 200 nm.

Abstract translation: 一种平均二极管，包括布置在半导体区域的表面处的相反导电类型的两个重掺杂区域之间的轻掺杂区域，重掺杂区域之间的轻掺杂区域的长度L大约在50和 200nm。

公开(公告)号：US09000840B2

公开(公告)日：2015-04-07

申请号：US14134167

申请日：2013-12-19

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Yvain Thonnart ,  Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel

IPC: H01L25/00 ,  H03K3/012 ,  G05F3/02 ,  H01L27/12 ,  H01L21/84 ,  H01L27/02 ,  H01L27/118 ,  H01L29/786

CPC classification number: H03K3/012 ,  G05F3/02 ,  G06F1/10 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648

Abstract: An integrated with a block including first and second oppositely doped semiconductor wells. There are standard cells placed next to one another, each standard cell including first transistors and a clock tree cell encircled by standard cells. The clock tree cell has a third semiconductor well with the same doping type as the doping of the first well and second transistors. The clock tree cell also has a semiconductor strip extending continuously around the third well and having the opposite doping type to the doping of the third well to electrically isolate the third well from the first well.

Abstract translation: 与包括第一和第二相对掺杂的半导体阱的块集成。 存在彼此相邻放置的标准单元，每个标准单元包括第一晶体管和由标准单元包围的时钟树单元。 时钟树单元具有与第一阱和第二晶体管的掺杂相同的掺杂类型的第三半导体阱。 时钟树单元还具有围绕第三阱连续延伸的半导体条，并且具有与第三阱的掺杂相反的掺杂类型，以将第三阱与第一阱电隔离。

公开(公告)号：US20150091106A1

公开(公告)日：2015-04-02

申请号：US14498091

申请日：2014-09-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： SÉBASTIEN BARNOLA ,  YVES MORAND ,  HEIMANU NIEBOJEWSKI

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L29/42372 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

Abstract translation: 一种方法包括在有源区的表面上形成栅极堆叠，包括沉积第一介电层; 沉积栅极导电层; 沉积第一金属层; 沉积第二金属层; 沉积第二电介质层; 部分地蚀刻栅极堆叠以在有源区上形成栅极区; 在活动区域​​上的栅极区域的任一侧上制造绝缘垫片; 制造源极和漏极区域; 在源极和漏极区域的表面上形成硅化物区域; 在活性区域的栅极区域中蚀刻在第一金属层上停止的第二介电层和第二金属层，以在绝缘间隔物之间​​形成空腔; 在活动区域​​上的栅极区域的第一金属层的表面上形成保护塞，其中保护塞填充空腔。

公开(公告)号：US08962399B2

公开(公告)日：2015-02-24

申请号：US14177593

申请日：2014-02-11

Applicant: Commissariat a l'Energie Atomique et aux Ene Alt ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Maud Vinet ,  Yves Morand ,  Heimanu Niebojewski

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762

CPC classification number: H01L29/66477 ,  H01L21/02236 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/76272 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/1207

Abstract: A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.

Abstract translation: 提供一种用于制造半导体层的半导体层的方法，所述半导体层具有至少两个不同厚度的绝缘体上的半导体层，包括至少一个其上连续设置有绝缘层和第一半导体层的基板，所述方法包括蚀刻第一层 使得所述层是连续的并且包括至少一个具有小于至少一个第二区域的厚度的第一区域; 氧化第一层以在其表面上形成电绝缘氧化膜，使得在第一区域中，氧化膜延伸至绝缘层; 部分地除去氧化膜以露出第一区域外的第一层; 在所述堆叠上形成第二半导体层，以与所述第一层形成具有与所述第一和第二区域的厚度不同的厚度的第三连续半导体层。

公开(公告)号：US20150035106A1

公开(公告)日：2015-02-05

申请号：US14446804

申请日：2014-07-30

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Jean-Pierre Carrere ,  Patrick Gros D'Aillon ,  Stephane Allegret-Maret ,  Jean-Pierre Oddou

IPC: H01L27/146

CPC classification number: H01L27/14625 ,  H01L27/1462 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685

Abstract: An integrated circuit includes a back side illuminated image sensor formed by a substrate supporting at least one pixel, an interconnect part situated above a front side of the substrate and an anti-reflective layer situated above a back side of the substrate. The anti-reflective layer may be formed of a silicon nitride layer. An additional layer is situated above the anti-reflective layer. The additional layer is formed of one of amorphous silicon nitride or hydrogenated amorphous silicon nitride, in which the ratio of the number of silicon atoms per cubic centimeter to the number of nitrogen atoms per cubic centimeter is greater than 0.7.

Abstract translation: 集成电路包括由支撑至少一个像素的衬底形成的背面照明图像传感器，位于衬底前侧之上的互连部分和位于衬底背面上方的抗反射层。 抗反射层可以由氮化硅层形成。 附加层位于抗反射层上方。 附加层由非晶氮化硅或氢化非晶氮化硅之一形成，其中每立方厘米的硅原子数与每立方厘米的氮原子数之比大于0.7。

公开(公告)号：US20150022987A1

公开(公告)日：2015-01-22

申请号：US14330347

申请日：2014-07-14

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Sebastien Gallois-Garreignot ,  Jérôme Lopez ,  Gil Provent ,  Caroline Moutin ,  Vincent Fiori

IPC: H05K7/02 ,  H05K1/11

CPC classification number: H05K7/02 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H05K1/111 ,  H05K2201/10439 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: An electronic device includes an integrated circuit chip with an insulating passivation layer. An opening in the passivation layer uncovers a first region of an electrical contact. An electrical connection pad is formed to fill the opening by covering the first region and extend in projection in such a way as to cover a second region situated on the passivation layer surrounding the opening. The periphery of at least one of the first and second regions has an elongate or oblong shape. Centers of the opening and the pad are aligned with each other.

Abstract translation: 电子设备包括具有绝缘钝化层的集成电路芯片。 钝化层中的开口露出电接触的第一区域。 形成电连接垫以通过覆盖第一区域而填充开口，并且以突出方式延伸以覆盖位于围绕开口的钝化层上的第二区域。 第一和第二区域中的至少一个区域的周边具有细长或长方形形状。 开口和垫的中心彼此对准。