公开(公告)号：US20120218829A1

公开(公告)日：2012-08-30

申请号：US13467491

申请日：2012-05-09

Applicant: Jin-Ki KIM

Inventor： Jin-Ki KIM

IPC: G11C16/04

CPC classification number: G11C8/14 ,  G11C8/10 ,  G11C8/12 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C2211/5642

Abstract: A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector.

Abstract translation: 公开了一种NAND闪速存储器件。 NAND闪存器件包括被定义为多个扇区的NAND快闪存储器阵列。 行解码在两个级别执行。 执行适用于所有部门的第一级。 例如，这可以用于选择块。 例如，针对特定扇区执行第二级别，以选择特定扇区中的块内的页面。 对扇区内的页面的分辨率进行读取和编程操作，同时对扇区内的块的分辨率进行擦除操作。

公开(公告)号：US20120215967A1

公开(公告)日：2012-08-23

申请号：US13399587

申请日：2012-02-17

Applicant: Vinod Lakhani ,  Benjamin Louie

Inventor： Vinod Lakhani ,  Benjamin Louie

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G11C16/04 ,  G11C29/76 ,  G11C29/808 ,  G11C29/82

Abstract: An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

Abstract translation: 描述了一种改进的非易失性擦除块存储器件装置和方法，其包括改进的寻址方案以提供扩展寻址，以允许不用于修复要被访问和利用的主存储器阵列的一般使用擦除块的冗余擦除块作为 最终用户额外的存储空间。 由未使用的冗余擦除块形成的附加存储空间和主存储器阵列的指定存储空间作为单个相邻地址空间呈现给终端用户。 此外，冗余擦除块可以用于修复非易失性擦除块存储器或闪存设备的存储器阵列中的任何损坏的擦除块，而不管银行放置。

公开(公告)号：US08230147B2

公开(公告)日：2012-07-24

申请号：US12784238

申请日：2010-05-20

Applicant: HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G06F13/00 ,  G06F1/12 ,  G06F12/00 ,  G11C7/00

CPC classification number: G11C7/10 ,  G06F13/1689

Abstract: A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and a memory location. The target device responds to the read command to read data in the location identified by the memory location. Read data is provided as an output signal that is transmitted from a last device in the serial interconnection to a data receiver of the controller. The data receiver establishes acquisition instants relating to clocks in consideration of a total flow-through latency in the serial interconnection. Where each device has a clock synchronizer, a propagated clock signal through the serial interconnection is used for establishing the acquisition instants. The read data is latched in response to the established acquisition instants in consideration of the flow-through latency, valid data is latched in the data receiver.

Abstract translation: 系统控制器与串行互连中的设备通信。 系统控制器发送读取命令，标识串行互连中的目标设备的设备地址和存储器位置。 目标设备响应读取命令以读取由存储器位置识别的位置中的数据。 读取数据被提供为从串行互连中的最后一个设备发送到控制器的数据接收器的输出信号。 考虑到串行互连中的总流通延迟，数据接收器建立与时钟有关的采集时刻。 在每个设备具有时钟同步器的情况下，通过串行互连的传播时钟信号用于建立采集时刻。 考虑到流通延迟，响应于建立的采集时刻来读取数据被锁存，有效数据被锁存在数据接收器中。

公开(公告)号：US20120185908A1

公开(公告)日：2012-07-19

申请号：US13351874

申请日：2012-01-17

Applicant: Yehuda BINDER

Inventor： Yehuda BINDER

IPC: H04N21/00

CPC classification number: H04L41/0836 ,  G05B2219/21039 ,  G05B2219/25181 ,  H04L12/40 ,  H04L12/40019 ,  H04L12/403 ,  H04L12/42 ,  H04L12/66 ,  H04L49/40

Abstract: A network for carrying out control, sensing and data communications, composed of a plurality of nodes. Each node may be connected to a payload, which includes sensors, actuators and DTE's. The network is formed using a plurality of independent communication links, each based on electrically-conducting communication media composed of at least two conductors and interconnecting two nodes, in a point-to-point configuration. During network operation, nodes can be dynamically configured as either data-generating nodes, wherein data is generated and transmitted into the network, or as receiver/repeater/router nodes, wherein received data is repeated from a receiver port to all output ports.

Abstract translation: 用于执行由多个节点组成的控制，感测和数据通信的网络。 每个节点可以连接到有效载荷，其中包括传感器，执行器和DTE。 网络使用多个独立的通信链路形成，每个通信链路基于由至少两个导体组成的导电通信介质并且以点对点配置互连两个节点。 在网络操作期间，节点可以被动态地配置为数据生成节点，其中数据被生成并发送到网络，或者作为接收器/中继器/路由器节点，其中接收的数据从接收器端口重复到所有的输出端口。

公开(公告)号：US08222930B2

公开(公告)日：2012-07-17

申请号：US12552040

申请日：2009-09-01

Applicant: Hong Beom Pyeon ,  Peter Vlasenko

Inventor： Hong Beom Pyeon ,  Peter Vlasenko

IPC: H03L7/00

CPC classification number: G06F1/24 ,  G06F1/3203 ,  H02J9/005

Abstract: A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode.

Abstract translation: 一种在省电模式下降低功耗的上电电路，同时保持表示电源电压令人满意的有效标志信号。 这是通过在省电模式期间关闭上电电路并且使用状态保持电路来响应于掉电信号来维持有效标志信号来实现的。 状态保持电路响应于上电电路的内部节点，以在内部节点达到预定电平时产生有效标志信号。 掉电信号可以是睡眠模式信号和深度掉电信号中的一个或两个。 状态保持包括用于将有效标志信号保持在省电模式中的超控电路，以及用于在省电模式退出时至少快速复位上电电路的内部节点的恢复电路。

公开(公告)号：US08199598B2

公开(公告)日：2012-06-12

申请号：US12882931

申请日：2010-09-15

Applicant: HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract translation: 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

公开(公告)号：US08194456B2

公开(公告)日：2012-06-05

申请号：US12617459

申请日：2009-11-12

Applicant: Jin-Ki Kim ,  Peter Gillingham

Inventor： Jin-Ki Kim ,  Peter Gillingham

IPC: G11C16/00

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

公开(公告)号：US20120120549A1

公开(公告)日：2012-05-17

申请号：US13293778

申请日：2011-11-10

Applicant: Cem Basceri ,  Gurtej S. Sandhu

Inventor： Cem Basceri ,  Gurtej S. Sandhu

IPC: H01G9/00

CPC classification number: H01L21/0228 ,  C23C16/029 ,  C23C16/18 ,  C23C16/405 ,  C23C16/45525 ,  H01L21/02183 ,  H01L21/28562 ,  H01L21/31604 ,  H01L21/31683 ,  H01L28/40 ,  H01L28/60 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: An interface forming method includes forming a first layer containing a first chemical element and chemisorbing on the first layer an interface layer containing at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element. A second layer comprising the second chemical element can be formed on the interface layer. The first layer might not substantially contain the second chemical element, the second layer might not substantially contain the first chemical element, or both. An apparatus can include a first layer containing a first chemical element, an interface layer chemisorbed on the first layer, and a second layer containing a second element on the interface layer. The interface layer can contain at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element.

Abstract translation: 界面形成方法包括在第一层上形成含有第一化学元素和化学吸附的第一层，所述界面层含有与第一化学元素不同的第二化学元素混合的第一化学元素的至少一个单层。 包含第二化学元素的第二层可以形成在界面层上。 第一层可能基本上不包含第二化学元素，第二层可能基本上不含有第一化学元素，或两者都不包含。 装置可以包括含有第一化学元素的第一层，在第一层上化学吸附的界面层和在界面层上含有第二元素的第二层。 界面层可以包含与第一化学元素不同的第二化学元素混合的第一化学元素的至少一个单层。

公开(公告)号：US08179786B2

公开(公告)日：2012-05-15

申请号：US11048370

申请日：2005-01-31

Applicant: Abdelhakim Hafid ,  Narayanan Natarajan ,  Shrirang Gadgil

Inventor： Abdelhakim Hafid ,  Narayanan Natarajan ,  Shrirang Gadgil

IPC: G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04J3/16 ,  H04J3/22 ,  H04L1/00 ,  H04L12/26 ,  H04L12/28 ,  H04L12/56

CPC classification number: H04L5/0064 ,  H04L41/0654 ,  H04L41/0896 ,  H04L41/12 ,  H04L45/00 ,  H04L45/22 ,  H04L45/24 ,  H04L45/28 ,  H04L45/302 ,  H04L45/50 ,  H04L47/15 ,  H04L47/2408 ,  H04L47/70 ,  H04L47/746 ,  H04L47/762 ,  H04L47/781 ,  H04L47/822 ,  H04L47/825 ,  H04L47/829

Abstract: At least one substitute path is provided in place of a plurality of existing paths of a network to reallocate traffic carried by the plurality of existing paths. The total bandwidth needed to carry the traffic of the plurality of existing paths is determined. A proposed route is generated from the available links in the network. A portion of the bandwidth of a proposed route may be allocated to the needed bandwidth when the bandwidth of a proposed route is greater than or equal to the needed bandwidth. When the bandwidth of the proposed route is less than the needed bandwidth, at least one further route is generated, and the needed bandwidth is divided among the proposed route and the at least one further route such that a minimum number of further routes are generated.

Abstract translation: 提供至少一个替代路径来代替网络的多个现有路径以重新分配由多个现有路径携带的业务。 确定承载多个现有路径的业务所需的总带宽。 所提出的路由是从网络中的可用链路生成的。 当所提出的路由的带宽大于或等于所需带宽时，所提出的路由的一部分带宽可以被分配给所需的带宽。 当所提出的路由的带宽小于所需的带宽时，生成至少一个另外的路由，并且在所提出的路由和所述至少一个另外的路由之间划分所需的带宽，使得生成最小数量的其他路由。

公开(公告)号：US08169849B2

公开(公告)日：2012-05-01

申请号：US12412968

申请日：2009-03-27

Applicant: Hong Pyeon Pyeon ,  HakJune Oh ,  Jin-Ki Kim

Inventor： Hong Pyeon Pyeon ,  HakJune Oh ,  Jin-Ki Kim

IPC: G11C8/00

CPC classification number: G11C7/1045 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/1078 ,  G11C2207/107

Abstract: Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a parallel link. Where input and output controls are received independently for each link for serial mode, a single set of input and output controls is used in common by all of the links during parallel mode.

Abstract translation: 提供了允许使用串行访问或使用并行访问来执行访问一个或多个存储体的方法和系统。 在串行模式下，每个链路都作为一个独立的串行链路运行。 相比之下，在串行模式下，链路作为并行链路共同工作。 在为串行模式的每个链路独立接收输入和输出控制的情况下，在并行模式期间，所有链路都使用一组输入和输出控制。