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    Integrated circuit having pairs of parallel complementary FinFETs
    61.
    发明授权
    Integrated circuit having pairs of parallel complementary FinFETs 失效
    具有成对的并联互补FinFET的集成电路

    公开(公告)号：US07517806B2

    公开(公告)日：2009-04-14

    申请号：US11186748

    申请日：2005-07-21

    Applicant: Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

    Inventor： Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

    IPC: H01L21/302

    CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823821 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

    Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.

    Abstract translation: 公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。 绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。 本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。 栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。 第一鳍片和第二鳍片具有大致相同的宽度。

    IMAGE SENSOR INCLUDING SPATIALLY DIFFERENT ACTIVE AND DARK PIXEL INTERCONNECT PATTERNS
    64.
    发明申请
    IMAGE SENSOR INCLUDING SPATIALLY DIFFERENT ACTIVE AND DARK PIXEL INTERCONNECT PATTERNS 有权
    图像传感器包括空间不同的主动和深色像素互连图案

    公开(公告)号：US20080111159A1

    公开(公告)日：2008-05-15

    申请号：US11560019

    申请日：2006-11-15

    Applicant: Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

    Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

    IPC: H01L31/101 ,  H01L29/765 ,  H01L23/52 ,  H01L21/339

    CPC classification number: H01L27/14636 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14687

    Abstract: An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

    Abstract translation: 互连布局，包括互连布局的图像传感器和用于制造图像传感器的方法各自使用有源像素区域内的第一电活性物理互连布局图案和在空间上不同于第一电活动的第二电活动物理互连布局图案 物理互连布局图案在暗像素区域内。 第二电活动物理互连布局图案包括插入在遮光层和在其下对准的光电传感器区域之间的至少一个电活动互连层，因此通常提供更高的布线密度。 在第二布局图案中更高的布线密度提供了图像传感器可以制造成具有增强的制造效率和金属化水平的降低。

    Pixel sensor having doped isolation structure sidewall
    65.
    发明授权
    Pixel sensor having doped isolation structure sidewall 有权
    具有掺杂隔离结构侧壁的像素传感器

    公开(公告)号：US07141836B1

    公开(公告)日：2006-11-28

    申请号：US10908885

    申请日：2005-05-31

    Applicant: James W. Adkisson ,  Mark D. Jaffe ,  Robert K. Leidy

    Inventor： James W. Adkisson ,  Mark D. Jaffe ,  Robert K. Leidy

    IPC: H01L27/148

    CPC classification number: H01L27/14603 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14683

    Abstract: A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. An isolation structure is formed adjacent to the photosensitive device pinning layer. The isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the isolation structure are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material.

    Abstract translation: 形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。 在光敏器件钉扎层附近形成隔离结构。 隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。 用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散工艺，由此在退火期间，存在于沿隔离结构中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。 替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来执行。

    DISCONTINUOUS GUARD RING
    69.
    发明申请
    DISCONTINUOUS GUARD RING 有权
    不连续的保护环

    公开(公告)号：US20130256826A1

    公开(公告)日：2013-10-03

    申请号：US13437273

    申请日：2012-04-02

    Applicant: Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

    Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

    IPC: H01L29/06

    CPC classification number: H01L29/0619 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.

    Abstract translation: 一种集成电路芯片，包括形成在半导体衬底上的保护环，所述保护环围绕所述集成电路芯片的有源区并且从所述半导体衬底延伸通过多个布线层中的一个或多个。 保护环包括堆叠金属线，空间分开各个金属线。 每个空间可以被形成为使得其部分地覆盖金属线中的空间直接在下方，但不覆盖任何其它空间。 或者，每个空间也可以形成为使得每个空间至少完全覆盖在其下面的金属线中的空间。

    Passivated through wafer vias in low-doped semiconductor substrates
    70.
    发明授权
    Passivated through wafer vias in low-doped semiconductor substrates 有权
    在低掺杂半导体衬底中通过晶片通孔钝化

    公开(公告)号：US08492272B2

    公开(公告)日：2013-07-23

    申请号：US13193991

    申请日：2011-07-29

    Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alvin J. Joseph

    Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alvin J. Joseph

    IPC: H01L21/4763 ,  H01L21/04 ,  H01L29/40

    CPC classification number: H01L21/76898 ,  H01L21/26586 ,  H01L29/732

    Abstract: A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.

    Abstract translation: 用于形成钝化的晶片通孔的方法，通过晶片通孔结构钝化，并通过设计结构钝化通过晶片。 该方法包括：在半导体衬底中形成贯穿晶片通孔，所述贯通晶片通孔包括从半导体衬底的顶部延伸到半导体衬底的底表面的电导体; 并且形成邻接电导体的所有侧壁的掺杂层，与半导体衬底相同的掺杂剂类型的掺杂层，掺杂层中掺杂剂的浓度大于半导体衬底中掺杂剂的浓度，掺杂层介于 电导体和半导体衬底。

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