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    PRUNING OF LOW POWER STATE INFORMATION FOR A PROCESSOR
    64.
    发明申请
    PRUNING OF LOW POWER STATE INFORMATION FOR A PROCESSOR 有权
    处理器的低功率状态信息的调整

    公开(公告)号：US20160246360A1

    公开(公告)日：2016-08-25

    申请号：US14630687

    申请日：2015-02-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Derek Hower ,  Marc Orr

    IPC: G06F1/32

    CPC classification number: G06F1/3293 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/46 ,  Y02D10/122 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A processor prunes state information based on information provided by software, thereby reducing the amount of state information to be stored prior to the processor entering a low-power state. The software, such as an operating system or application program executing at the processor, indicates one or more registers of the processor as storing data that is no longer useful. When preparing to enter the low-power state, the processor omits the indicated registers from the state information stored to memory.

    Abstract translation: 处理器基于由软件提供的信息来修剪状态信息，从而减少在处理器进入低功率状态之前要存储的状态信息量。 诸如在处理器执行的操作系统或应用程序的软件将处理器的一个或多个寄存器指示为不再有用的存储数据。 当准备进入低功率状态时，处理器从存储到存储器的状态信息中省略指示的寄存器。

    TRAFFIC RATE CONTROL FOR INTER-CLASS DATA MIGRATION IN A MULTICLASS MEMORY SYSTEM
    66.
    发明申请
    TRAFFIC RATE CONTROL FOR INTER-CLASS DATA MIGRATION IN A MULTICLASS MEMORY SYSTEM 有权
    用于多行存储器系统中的类间数据迁移的交通费率控制

    公开(公告)号：US20160170919A1

    公开(公告)日：2016-06-16

    申请号：US14569825

    申请日：2014-12-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sergey Blagodurov ,  Gabriel H. Loh ,  Yasuko Eckert

    IPC: G06F13/16 ,  G06F11/34 ,  G06F12/02

    CPC classification number: G06F13/1694 ,  G06F11/3414 ,  G06F12/023 ,  G06F13/161 ,  G06F2212/1044 ,  Y02D10/14

    Abstract: A system includes a plurality of memory classes and a set of one or more processing units coupled to the plurality of memory classes. The system further includes a data migration controller to select a traffic rate as a maximum traffic rate for transferring data between the plurality of memory classes based on a net benefit metric associated with the traffic rate, and to enforce the maximum traffic rate for transferring data between the plurality of memory classes.

    Abstract translation: 系统包括多个存储器类别以及耦合到多个存储器类别的一个或多个处理单元的集合。 该系统还包括数据迁移控制器，用于基于与业务速率相关联的净利益度量来选择业务速率作为用于在多个存储器类之间传送数据的最大业务速率，并且执行用于在数据传输之间传送数据的最大业务速率 多个存储器类。

    DECOUPLED ENTRY AND EXIT PREDICTION FOR POWER GATING
    68.
    发明申请
    DECOUPLED ENTRY AND EXIT PREDICTION FOR POWER GATING 有权
    放弃进入和退出预测功率增益

    公开(公告)号：US20150370311A1

    公开(公告)日：2015-12-24

    申请号：US14310908

    申请日：2014-06-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Manish Arora ,  Indrani Paul

    IPC: G06F1/32 ,  G06N5/04

    CPC classification number: G06F1/3296 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3293 ,  G06N5/04 ,  Y02D10/171 ,  Y02D50/20

    Abstract: Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. The entry/exit power gating logic also selectively implements one or more exit prediction techniques for exiting the power gated state based on estimates of reliability of the exit prediction techniques.

    Abstract translation: 电源门控逻辑检测处理设备的组件转换到空闲状态。 响应于检测到转换，入口/出口功率门控逻辑基于入口预测技术的可靠性的估计，选择性地实现用于功率门控组件的一个或多个入口预测技术。 入口/出口电力门控逻辑还基于对退出预测技术的可靠性的估计，选择性地实现一个或多个退出预测技术以退出电力门控状态。

    Idle phase exit prediction
    69.
    发明授权
    Idle phase exit prediction 有权
    空闲相位退出预测

    公开(公告)号：US09110671B2

    公开(公告)日：2015-08-18

    申请号：US13724599

    申请日：2012-12-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Srilatha Manne ,  William L Bircher ,  Mahdu S. S. Govindan ,  Michael J Schulte ,  Manish Arora

    IPC: G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

    Abstract: A method and apparatus for exiting a low power state based on a prior prediction is disclosed. An integrated circuit (IC) includes a functional unit configured to, during operation, cycle between intervals of an active state and intervals of an idle state. The IC also include a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state. The power management unit is further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power. The predetermined time is based on a prediction of idle state duration made prior to entering the low power state. The prediction may be generated by a prediction unit, based on a history of durations of intervals in which the functional unit was in the idle state.

    Abstract translation: 公开了一种基于先前预测退出低功率状态的方法和装置。 集成电路（IC）包括功能单元，其被配置为在操作期间在活动状态的间隔和空闲状态的间隔之间循环。 IC还包括电源管理单元，其被配置为响应于功能单元进入空闲状态而将功能单元置于低功率状态。 电源管理单元还被配置为在进入低功率之后的预定时间，预先使功能单元退出低功率状态。 预定时间基于在进入低功率状态之前进行的空闲状态持续时间的预测。 预测可以由预测单元基于功能单元处于空闲状态的间隔的持续时间的历史来生成。

    CONFIGURING PROCESSOR POLICIES BASED ON PREDICTED DURATIONS OF ACTIVE PERFORMANCE STATES
    70.
    发明申请
    CONFIGURING PROCESSOR POLICIES BASED ON PREDICTED DURATIONS OF ACTIVE PERFORMANCE STATES 审中-公开
    基于预期活跃绩效状态的配置处理者政策

    公开(公告)号：US20150186160A1

    公开(公告)日：2015-07-02

    申请号：US14146588

    申请日：2014-01-02

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne

    IPC: G06F9/445 ,  G06F11/34 ,  G06F12/08

    CPC classification number: G06F11/3423 ,  G06F1/3243 ,  G06F11/3452 ,  G06F12/0804 ,  G06F12/0864 ,  G06F2212/601 ,  Y02D10/152 ,  Y02D10/34 ,  Y02D50/20

    Abstract: Durations of active performance states of components of a processing system can be predicted based on one or more previous durations of an active state of the components. One or more entities in the processing system such as processor cores or caches can be configured based on the predicted durations of the active state of the components. Some embodiments configure a first component in a processing system based on a predicted duration of an active state of a second component of the processing system. The predicted duration is predicted based on one or more previous durations of an active state of the second component.

    Abstract translation: 可以基于组件的活动状态的一个或多个先前持续时间来预测处理系统的组件的主动性能状态的持续时间。 可以基于组件的活动状态的预测持续时间来配置处理系统中的一个或多个实体，例如处理器核心或高速缓存。 一些实施例基于处理系统的第二组件的活动状态的预测持续时间来配置处理系统中的第一组件。 基于第二组件的活动状态的一个或多个先前持续时间预测预测持续时间。

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