公开(公告)号：US09478434B2

公开(公告)日：2016-10-25

申请号：US14543683

申请日：2014-11-17

Applicant: Applied Materials, Inc.

Inventor： Xikun Wang ,  Mandar Pandit ,  Zhenjiang Cui ,  Mikhail Korolik ,  Anchuan Wang ,  Nitin K. Ingle ,  Jie Liu

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC classification number: H01L21/31122 ,  H01J37/32357 ,  H01L21/02063 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139

Abstract: A method of removing titanium nitride hardmask is described. The hardmask resides above a low-k dielectric layer prior to removal and the low-k dielectric layer retains a relatively low net dielectric constant after the removal process. The low-k dielectric layer may be part of a dual damascene structure having copper at the bottom of the vias. A non-porous carbon layer is deposited prior to the titanium nitride hardmask removal to protect the low-k dielectric layer and the copper. The titanium nitride hardmask is removed with a gas-phase etch using plasma effluents formed in a remote plasma from a chlorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride.

Abstract translation: 描述了一种去除氮化钛硬掩模的方法。 在去除之前，硬掩模位于低k电介质层之上，并且低k电介质层在除去过程之后保持相对较低的净介电常数。 低k电介质层可以是在通孔底部具有铜的双镶嵌结构的一部分。 在氮化钛硬掩模去除之前沉积无孔碳层以保护低k电介质层和铜。 使用在含氯前体的远程等离子体中形成的等离子体流出物，用气相蚀刻去除氮化钛硬掩模。 远程等离子体内的等离子体流出物流入基板处理区域，其中等离子体流出物与氮化钛反应。

公开(公告)号：US09472417B2

公开(公告)日：2016-10-18

申请号：US14513517

申请日：2014-10-14

Applicant: Applied Materials, Inc.

Inventor： Nitin K. Ingle ,  Jessica Sevanne Kachian ,  Lin Xu ,  Soonam Park ,  Xikun Wang ,  Jeffrey W. Anthis

IPC: H01L21/311 ,  H01L21/3065 ,  H01L21/02 ,  C23F1/02 ,  C23F1/12 ,  H01J37/32 ,  C23F4/00 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/3065 ,  C23F1/02 ,  C23F1/12 ,  C23F4/00 ,  H01J37/3244 ,  H01J2237/334 ,  H01J2237/3341 ,  H01L21/02071 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/76814

Abstract: Methods of selectively etching metal-containing materials from the surface of a substrate are described. The etch selectively removes metal-containing materials relative to silicon-containing films such as silicon, polysilicon, silicon oxide, silicon germanium, silicon carbide, silicon carbon nitride and/or silicon nitride. The methods include exposing metal-containing materials to halogen containing species in a substrate processing region. No plasma excites the halogen-containing precursor either remotely or locally in embodiments.

Abstract translation: 描述了从衬底表面选择性地蚀刻含金属材料的方法。 蚀刻相对于含硅膜如硅，多晶硅，氧化硅，硅锗，碳化硅，氮化硅和/或氮化硅选择性去除含金属的材料。 这些方法包括将含金属的材料暴露于基底处理区域中含有卤素的物质。 在实施例中，没有等离子体远程地或局部地激发含卤素的前体。

公开(公告)号：US09449845B2

公开(公告)日：2016-09-20

申请号：US14584099

申请日：2014-12-29

Applicant: Applied Materials, Inc.

Inventor： Jie Liu ,  Jingchun Zhang ,  Anchuan Wang ,  Nitin K. Ingle ,  Seung Park ,  Zhijun Chen ,  Ching-Mei Hsu

IPC: H01L21/302 ,  H01L21/3213 ,  H01J37/32

CPC classification number: H01L21/32136 ,  H01J37/32357

Abstract: Methods of etching exposed titanium nitride with respect to other materials on patterned heterogeneous structures are described, and may include a remote plasma etch formed from a fluorine-containing precursor. Precursor combinations including plasma effluents from the remote plasma are flowed into a substrate processing region to etch the patterned structures with high titanium nitride selectivity under a variety of operating conditions. The methods may be used to remove titanium nitride at faster rates than a variety of metal, nitride, and oxide compounds.

Abstract translation: 描述了相对于图案化异质结构上的其它材料蚀刻暴露的氮化钛的方法，并且可以包括由含氟前体形成的远程等离子体蚀刻。 包括来自远程等离子体的等离子体流出物的前体组合流入基板处理区域以在各种操作条件下以高氮化钛选择性蚀刻图案化结构。 该方法可用于以比各种金属，氮化物和氧化物化合物更快的速率除去氮化钛。

公开(公告)号：US20160218018A1

公开(公告)日：2016-07-28

申请号：US14607883

申请日：2015-01-28

Applicant: Applied Materials, Inc.

Inventor： Jie Liu ,  Vinod R. Purayath ,  Xikun Wang ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/3213 ,  H01L27/115 ,  H01L21/8234

CPC classification number: H01L21/32136 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32954 ,  H01L21/32135 ,  H01L21/823437 ,  H01L27/11582

Abstract: Methods of selectively etching tungsten from the surface of a patterned substrate are described. The methods electrically separate vertically arranged tungsten slabs from one another as needed. The vertically arranged tungsten slabs may form the walls of a trench during manufacture of a vertical flash memory cell. The tungsten etch may selectively remove tungsten relative to films such as silicon, polysilicon, silicon oxide, aluminum oxide, titanium nitride and silicon nitride. The methods include exposing electrically-shorted tungsten slabs to remotely-excited fluorine formed in a remote plasma region. Process parameters are provided which result in uniform tungsten recess within the trench. A low electron temperature is maintained in the substrate processing region to achieve high etch selectivity and uniform removal throughout the trench.

Abstract translation: 描述了从图案化衬底的表面选择性地蚀刻钨的方法。 所述方法根据需要将垂直排列的钨板彼此电分离。 在垂直闪存单元的制造期间，垂直布置的钨板可以形成沟槽的壁。 钨蚀刻可以相对于诸如硅，多晶硅，氧化硅，氧化铝，氮化钛和氮化硅的膜选择性地去除钨。 这些方法包括将电短路钨板暴露于在远程等离子体区域中形成的远程激发的氟。 提供了在沟槽内产生均匀的钨凹槽的工艺参数。 在基板处理区域中保持低电子温度，以实现高蚀刻选择性并且在整个沟槽中均匀地去除。

公开(公告)号：US09373522B1

公开(公告)日：2016-06-21

申请号：US14603018

申请日：2015-01-22

Applicant: Applied Materials, Inc.

Inventor： Xikun Wang ,  Mandar Pandit ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/20 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76807 ,  H01L21/76814

Abstract: A method of removing titanium nitride hardmask is described. The hardmask resides above a low-k dielectric layer prior to removal and the low-k dielectric layer retains a relatively low net dielectric constant after the removal process. The low-k dielectric layer may be part of a dual damascene structure having copper at the bottom of the vias. A non-porous carbon layer is deposited prior to the titanium nitride hardmask removal to protect the low-k dielectric layer and the copper. The titanium nitride hardmask and the non-porous carbon layer are removed with a gas-phase etch using plasma effluents formed in a remote plasma from a chlorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents react with the non-porous carbon layer and the titanium nitride.

Abstract translation: 描述了一种去除氮化钛硬掩模的方法。 在去除之前，硬掩模位于低k电介质层之上，并且低k电介质层在去除过程之后保持相对较低的净介电常数。 低k电介质层可以是在通孔底部具有铜的双镶嵌结构的一部分。 在氮化钛硬掩模去除之前沉积无孔碳层以保护低k电介质层和铜。 使用在含氯前体的远程等离子体中形成的等离子体流出物，通过气相蚀刻去除氮化钛硬掩模和无孔碳层。 远程等离子体内的等离子体流出物流入基板处理区域，其中等离子体流出物与无孔碳层和氮化钛反应。

公开(公告)号：US09355862B2

公开(公告)日：2016-05-31

申请号：US14543618

申请日：2014-11-17

Applicant: Applied Materials, Inc.

Inventor： Mandar Pandit ,  Xikun Wang ,  Zhenjiang Cui ,  Mikhail Korolik ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/311

CPC classification number: H01L21/31122 ,  H01J37/32357 ,  H01L21/02063 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139

Abstract: A method of removing titanium nitride hardmask is described. The hardmask resides above a low-k dielectric layer prior to removal and the low-k dielectric layer retains a relatively low net dielectric constant after the removal process. The low-k dielectric layer may be part of a dual damascene structure having copper at the bottom of the vias. A non-porous carbon layer is deposited prior to the titanium nitride hardmask removal to protect the low-k dielectric layer and the copper. The titanium nitride hardmask is removed with a gas-phase etch using plasma effluents formed in a remote plasma from a fluorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride.

Abstract translation: 描述了一种去除氮化钛硬掩模的方法。 在去除之前，硬掩模位于低k电介质层之上，并且低k电介质层在去除过程之后保持相对较低的净介电常数。 低k电介质层可以是在通孔底部具有铜的双镶嵌结构的一部分。 在氮化钛硬掩模去除之前沉积无孔碳层以保护低k电介质层和铜。 使用从含氟前体的远程等离子体中形成的等离子体流出物，用气相蚀刻去除氮化钛硬掩模。 远程等离子体内的等离子体流出物流入基板处理区域，其中等离子体流出物与氮化钛反应。

公开(公告)号：US09343293B2

公开(公告)日：2016-05-17

申请号：US13934863

申请日：2013-07-03

Applicant: Applied Materials, Inc.

Inventor： Brian Saxton Underwood ,  Abhijit Basu Mallick ,  Nitin K. Ingle

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/452 ,  C23C16/455

CPC classification number: H01L21/02216 ,  C23C16/401 ,  C23C16/452 ,  C23C16/45565 ,  C23C16/45574 ,  H01L21/02126 ,  H01L21/02208 ,  H01L21/02274

Abstract: Methods are described for forming a dielectric layer on a patterned substrate. The methods may include combining a silicon-and-carbon-containing precursor and a radical oxygen precursor in a plasma free substrate processing region within a chemical vapor deposition chamber. The silicon-and-carbon-containing precursor and the radical oxygen precursor react to deposit a flowable silicon-carbon-oxygen layer on the patterned substrate. The resulting film possesses a low wet etch rate ratio relative to thermal silicon oxide and other standard dielectrics.

Abstract translation: 描述了在图案化衬底上形成电介质层的方法。 所述方法可以包括在化学气相沉积室内的无等离子体衬底处理区域中组合含硅和碳的前体和自由基氧前体。 含硅和碳的前体和自由基氧前体反应以在图案化的衬底上沉积可流动的硅 - 碳 - 氧层。 所得膜相对于热氧化硅和其它标准电介质具有低的湿蚀刻速率比。

公开(公告)号：US20160064233A1

公开(公告)日：2016-03-03

申请号：US14936448

申请日：2015-11-09

Applicant: Applied Materials, Inc.

Inventor： Anchuan Wang ,  Xinglong Chen ,  Zihui Li ,  Hiroshi Hamana ,  Zhijun Chen ,  Ching-Mei Hsu ,  Jiayin Huang ,  Nitin K. Ingle ,  Dmitry Lubomirsky ,  Shankar Venkataraman ,  Randhir Thakur

IPC: H01L21/3065

CPC classification number: H01L21/324 ,  C23C16/4405 ,  H01J37/32357 ,  H01J37/32862 ,  H01L21/02041 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/263 ,  H01L21/2686 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/67069 ,  H01L21/67075 ,  H01L21/6708 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/67184 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/67288 ,  H01L21/67703 ,  H01L21/67739 ,  H01L21/67742 ,  H01L21/6831

Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

公开(公告)号：US09275834B1

公开(公告)日：2016-03-01

申请号：US14627991

申请日：2015-02-20

Applicant: Applied Materials, Inc.

Inventor： Seung Park ,  Mikhail Korolik ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/3065 ,  H01J37/32

CPC classification number: H01L21/3065 ,  H01J37/32357 ,  H01J37/32366 ,  H01J37/3244 ,  H01L21/32136 ,  H01L21/32137

Abstract: A method of removing titanium nitride is described. The silicon nitride resides on a patterned substrate. The titanium nitride is removed with a gas-phase etch using plasma effluents formed in a remote plasma from a fluorine-containing precursor, a nitrogen-and-hydrogen-containing precursor and an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride.

Abstract translation: 描述了一种去除氮化钛的方法。 氮化硅位于图案化衬底上。 使用在含氟前体，含氮和氢的前体和含氧前体的远程等离子体中形成的等离子体流出物，通过气相蚀刻除去氮化钛。 远程等离子体内的等离子体流出物流入基板处理区域，其中等离子体流出物与氮化钛反应。

公开(公告)号：US09263278B2

公开(公告)日：2016-02-16

申请号：US14230590

申请日：2014-03-31

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/3065 ,  H01J37/00 ,  H01L21/28 ,  H01L21/3213 ,  H01J37/32

CPC classification number: H01L21/28273 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/32137

Abstract: Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.

Abstract translation: 描述了以两种不同蚀刻速率蚀刻两个掺杂硅部分的方法。 当两者都暴露并存在于相同的衬底上时，可以比p型硅部分蚀刻n型硅部分。 n型硅部分可以掺杂磷，并且p型硅部分可以掺杂硼。 在一个示例中，n型硅部分是单晶硅，p型硅部分是多晶硅（即多晶硅）。 p型硅部分可以是闪存单元中的多晶硅浮动栅极，并且可以位于栅极氧化硅的上方，栅极氧化硅又位于n型有源区单晶硅部分之上。 n型有源区硅部分的额外修整可以减少使用期间被捕获的电荷的积累并且增加闪存器件的寿命。