公开(公告)号：US20090218603A1

公开(公告)日：2009-09-03

申请号：US12463309

申请日：2009-05-08

申请人： Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau ,  Brian S. Doyle

发明人： Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau ,  Brian S. Doyle

IPC分类号： H01L29/04

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

摘要翻译： 描述了半导体膜的图案化方法。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

公开(公告)号：US20090149012A1

公开(公告)日：2009-06-11

申请号：US12369642

申请日：2009-02-11

申请人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

发明人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

IPC分类号： H01L21/4763

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

公开(公告)号：US20170040530A1

公开(公告)日：2017-02-09

申请号：US15333017

申请日：2016-10-24

申请人： Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Uday Shah ,  Elijah V. Karpov ,  Roksana Golizadeh Mojarad ,  Mark L. Doczy ,  Robert S. Chau

发明人： Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Uday Shah ,  Elijah V. Karpov ,  Roksana Golizadeh Mojarad ,  Mark L. Doczy ,  Robert S. Chau

IPC分类号： H01L43/10 ,  H01F10/16 ,  H01L43/12 ,  H01F10/14 ,  H01L27/22 ,  H01L43/08

CPC分类号： H01L43/10 ,  G11C11/161 ,  G11C11/18 ,  H01F10/14 ,  H01F10/16 ,  H01F10/1936 ,  H01F10/3236 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.

摘要翻译： 描述了具有增强的稳定性的垂直自旋转移转矩存储器（STTM）装置和制造具有增强的稳定性的垂直STTM装置的方法。 例如，用于磁隧道结的材料层堆叠包括固定磁性层。 电介质层设置在固定磁性层的上方。 自由磁性层设置在电介质层的上方。 导电氧化物材料层设置在自由磁性层上。

公开(公告)号：US20160293765A1

公开(公告)日：2016-10-06

申请号：US15182343

申请日：2016-06-14

申请人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

发明人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/51 ,  H01L29/04 ,  H01L29/66

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

公开(公告)号：US09190518B2

公开(公告)日：2015-11-17

申请号：US14273373

申请日：2014-05-08

申请人： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

发明人： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/423

CPC分类号： H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20150091058A1

公开(公告)日：2015-04-02

申请号：US14039696

申请日：2013-09-27

申请人： Brian S. Doyle ,  Uday Shah ,  Roza Kotlyar ,  Charles C. Kuo

发明人： Brian S. Doyle ,  Uday Shah ,  Roza Kotlyar ,  Charles C. Kuo

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/66666 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4983 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/7391 ,  H01L29/749 ,  H01L29/7827 ,  H01L29/7848

摘要： Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

摘要翻译： 描述垂直晶体管器件。 例如，在一个实施例中，垂直晶体管器件包括设置在衬底上的外延源半导体区域，设置在源极半导体区域上的外延沟道半导体区域，设置在沟道半导体区域上的外延漏极半导体区域和栅电极 区域围绕半导体沟道区域的侧壁。 至少一个半导体区域的组合物沿着相对于衬底的表面垂直的纵向轴线变化。

公开(公告)号：US20140035009A1

公开(公告)日：2014-02-06

申请号：US14048923

申请日：2013-10-08

申请人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

发明人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC分类号： H01L29/04

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

摘要翻译： 对半导体膜的图案化方法进行说明。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

公开(公告)号：US07579280B2

公开(公告)日：2009-08-25

申请号：US10859328

申请日：2004-06-01

申请人： Justin K. Brask ,  Brian S. Doyle ,  Uday Shah ,  Robert S. Chau

发明人： Justin K. Brask ,  Brian S. Doyle ,  Uday Shah ,  Robert S. Chau

IPC分类号： H01L21/311

CPC分类号： H01L21/31111 ,  H01L21/3081 ,  H01L21/76838 ,  H01L29/785

摘要： A method of patterning a thin film. The method includes forming a mask on a film to be patterned. The film is then etched in alignment with the mask to form a patterned film having a pair of laterally opposite sidewalls. A protective layer is formed on the pair of laterally opposite sidewalls. Next, the mask is removed from above the patterned film. After removing the mask from the patterned film, the protective layer is removed from the sidewalls.

摘要翻译： 图案化薄膜的方法。 该方法包括在待图案化的膜上形成掩模。 然后将膜与掩模对准地蚀刻以形成具有一对横向相对的侧壁的图案化膜。 在一对横向相对的侧壁上形成保护层。 接下来，从图案化膜的上方去除掩模。 在从图案化的膜去除掩模之后，从侧壁去除保护层。

公开(公告)号：US07521775B2

公开(公告)日：2009-04-21

申请号：US11452883

申请日：2006-06-13

申请人： Brian S. Doyle ,  Uday Shah ,  Been-Yih Jin ,  Jack T. Kavalieros

发明人： Brian S. Doyle ,  Uday Shah ,  Been-Yih Jin ,  Jack T. Kavalieros

IPC分类号： H01L29/06

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.

摘要翻译： 本发明的实施例包括与具有高k电介质的三维晶体管和金属栅极相关的装置和方法，其翅​​片由其顶表面上的硬掩模层保护。 在一个实施例中，硬掩模层包括氧化物。

公开(公告)号：US20090004868A1

公开(公告)日：2009-01-01

申请号：US11824489

申请日：2007-06-29

申请人： Brian S. Doyle ,  Uday Shah ,  Jack T. Kavalieros

发明人： Brian S. Doyle ,  Uday Shah ,  Jack T. Kavalieros

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L27/10861 ,  H01L28/90

摘要： In one embodiment, a method comprises forming a sacrificial amorphous silicon layer on a semiconductor substrate, forming a hardmask on the amorphous silicon layer, etching one or more lines in the sacrificial amorphous silicon layer, growing oxide structures on the amorphous silicon layer, and forming a trench in the semiconductor substrate between the oxide structures.

摘要翻译： 在一个实施例中，一种方法包括在半导体衬底上形成牺牲非晶硅层，在非晶硅层上形成硬掩模，蚀刻牺牲非晶硅层中的一条或多条线，在非晶硅层上生长氧化物结构，以及形成 氧化物结构之间的半导体衬底中的沟槽。