公开(公告)号：US07026207B2

公开(公告)日：2006-04-11

申请号：US10715611

申请日：2003-11-18

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： H01L21/8238

CPC分类号： H01L27/10888 ,  H01L21/76877 ,  H01L27/10894

摘要： A method of filling a bit line contact via. The method includes providing a substrate having a device region and periphery region, the device region having a transistor, having a gate electrode, drain region, and source region, on the substrate, forming a dielectric layer overlying the substrate, the dielectric layer having a bit line contact via exposing the drain region, and periphery contact via exposing the periphery region, forming a doped conductive layer, lower than the dielectric layer, overlying the drain region, conformally forming a barrier layer overlying the dielectric layer, doped conductive layer, and periphery region, and forming a first conductive layer filling the bit line contact via and periphery contact via.

摘要翻译： 填充位线接触通孔的方法。 该方法包括提供具有器件区域和外围区域的衬底，器件区域具有在衬底上的栅电极，漏极区和源极区的晶体管，形成覆盖衬底的电介质层，电介质层具有 通过暴露漏极区域和周边接触，通过暴露外围区域形成位线接触，形成覆盖漏极区域的低于介电层的掺杂导电层，保形地形成覆盖在电介质层上的阻挡层，掺杂导电层和 并且形成填充位线接触通孔和周边接触通孔的第一导电层。

公开(公告)号：US06998347B2

公开(公告)日：2006-02-14

申请号：US10605238

申请日：2003-09-17

申请人： Min-Yi Hsu ,  Hsin-Jung Ho ,  Kun-Shin Huang ,  Yi-Nan Chen ,  Kaanlu Tzou

发明人： Min-Yi Hsu ,  Hsin-Jung Ho ,  Kun-Shin Huang ,  Yi-Nan Chen ,  Kaanlu Tzou

IPC分类号： H01L21/302

CPC分类号： H01L21/02079 ,  H01L21/32134 ,  H01L21/32135

摘要： A method of reworking an integrated circuit device is described. A substrate having a dielectric layer, a barrier layer, a conductive layer and an anti-reflective layer formed thereon, is provided. The method of reworking the barrier layer, the conductive layer and the anti-reflective layer comprises removing the anti-reflection layer by performing a dry etching process, removing the conductive layer by performing a wet etching process, and then removing the barrier layer by performing a chemical machine polishing process.

摘要翻译： 描述了对集成电路器件进行返工的方法。 提供了具有形成在其上的电介质层，阻挡层，导电层和抗反射层的基板。 对阻挡层，导电层和抗反射层进行再加工的方法包括通过进行干蚀刻工艺去除抗反射层，通过进行湿蚀刻工艺去除导电层，然后通过执行 化学机械抛光工艺。

公开(公告)号：US20050277287A1

公开(公告)日：2005-12-15

申请号：US11019850

申请日：2004-12-21

申请人： Yi-Nan Chen ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： G03F9/00 ,  H01L21/00 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/544

CPC分类号： H01L21/31144 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/76802 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.

摘要翻译： 一种使用多层硬掩模形成接触孔的方法。 提供了具有器件区域和其中具有开口的对准区域用作对准标记的衬底。 形成覆盖在基板上的电介质层，并填充开口，随后是多层硬掩模。 开口上的多层硬掩模被部分去除，并且在器件区域上被图案化以在其中形成多个孔并且暴露下面的介电层。 在器件区域上暴露的介电层被蚀刻以在其中形成多个接触孔。

公开(公告)号：US20050277258A1

公开(公告)日：2005-12-15

申请号：US10940707

申请日：2004-09-15

申请人： Tse-Yao Huang ,  Kuo-Chien Wu ,  Yi-Nan Chen

发明人： Tse-Yao Huang ,  Kuo-Chien Wu ,  Yi-Nan Chen

IPC分类号： H01L21/02 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8239 ,  H01L27/10 ,  H01L27/105

CPC分类号： H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823871 ,  H01L27/105 ,  H01L27/1052

摘要： A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; forming a first insulating layer, which is then planarized to expose the nitride insulating layer on the gate structure; etching through the first insulating layer to form a first part of a contact hole; forming a first part of a contact in said first part of the contact hole; forming a second insulating layer; etching through the second insulating layer to form a second part of the contact hole; and forming a second part of the contact in the second part of the contact hole. The two-stage etching process for forming a conductive contact effectively prevents over-etching and short-circuiting between a wordline and a bitline.

摘要翻译： 一种用于在设置有多个场效应晶体管的半导体衬底上形成自对准接触的方法。 该方法包括以下步骤：在晶体管的栅极结构和扩散区上形成薄的氮化物绝缘层; 形成第一绝缘层，然后将其平坦化以暴露栅极结构上的氮化物绝缘层; 蚀刻穿过第一绝缘层以形成接触孔的第一部分; 在所述接触孔的所述第一部分中形成接触的第一部分; 形成第二绝缘层; 蚀刻穿过第二绝缘层以形成接触孔的第二部分; 以及在接触孔的第二部分中形成接触的第二部分。 用于形成导电接触的两级蚀刻工艺有效地防止了字线和位线之间的过蚀刻和短路。

公开(公告)号：US20050275111A1

公开(公告)日：2005-12-15

申请号：US10923585

申请日：2004-08-20

申请人： Wen-Kuei Hsieh ,  Hui-Min Mao ,  Yi-Nan Chen

发明人： Wen-Kuei Hsieh ,  Hui-Min Mao ,  Yi-Nan Chen

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L21/31144 ,  H01L21/76802 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon layer is formed on the dielectric layer, with over the opening on the alignment region comprising a recessed region and on the device region comprising a plurality of holes therein to expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form contact holes therein.

摘要翻译： 使用部分凹入的硬掩模形成接触孔的方法。 提供具有装置区域和其中具有开口的对准区域的基板，用作对准标记。 形成覆盖在基板上并填充开口的电介质层。 在电介质层上形成多晶硅层，其中对准区域上的开口包括凹陷区域，并且在其上包括多个孔的器件区域上露出下面的介电层。 蚀刻器件区域上的暴露的电介质层以在其中形成接触孔。

公开(公告)号：US06969881B2

公开(公告)日：2005-11-29

申请号：US10640100

申请日：2003-08-13

申请人： Ming-Cheng Chang ,  Yi-Chen Chen ,  Yi-Nan Chen

发明人： Ming-Cheng Chang ,  Yi-Chen Chen ,  Yi-Nan Chen

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L21/26586 ,  H01L27/10832 ,  H01L27/10838 ,  H01L27/10864 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/1037 ,  H01L29/78 ,  H01L29/945

摘要： A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.

摘要翻译： 局部垂直存储单元及其制造方法。 提供一种半导体衬底，其中分别形成具有深沟槽电容器的两个深沟槽，并且深沟槽电容器低于半导体衬底的顶表面。 在深沟槽外部的半导体的一部分被去除以在其之间形成柱。 柱被离子注入以在柱角中形成作为S / D区域的离子掺杂区域。 栅极电介质层和导电层依次形成在柱上。 在导电层旁边的半导体衬底中形成隔离。 导电层被限定为形成第一栅极和第二栅极。

公开(公告)号：US06960530B2

公开(公告)日：2005-11-01

申请号：US10724435

申请日：2003-11-28

申请人： Chang-Rong Wu ,  Yi-Nan Chen ,  Kuo-Chien Wu ,  Hung-Chang Liao

发明人： Chang-Rong Wu ,  Yi-Nan Chen ,  Kuo-Chien Wu ,  Hung-Chang Liao

IPC分类号： H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/76224 ,  H01L21/31116 ,  H01L21/31612

摘要： A method of reducing trench aspect ratio. A trench is formed in a substrate. A conformal Si-rich oxide layer is formed on the surface of the trench by HDPCVD. A conformal first oxide layer is formed on the Si-rich oxide layer by HDPCVD. A conformal second oxide layer is formed on the first oxide layer by LPCVD. Part of the Si-rich oxide layer, the second oxide layer and the first oxide layer are removed by anisotropic etching to form an oxide spacer composed of a remaining Si-rich oxide layer, a remaining second oxide layer and a remaining first oxide layer. The remaining second oxide layer, part of the remaining first oxide layer and part of the Si-rich oxide layer are removed by BOE. Thus, parts of the remaining first and Si-rich oxide layers are formed on the lower surface of the trench, thereby reducing the trench aspect ratio.

摘要翻译： 减小沟槽纵横比的方法。 在衬底中形成沟槽。 通过HDPCVD在沟槽的表面上形成共形的富Si氧化物层。 通过HDPCVD在富Si氧化物层上形成保形第一氧化物层。 通过LPCVD在第一氧化物层上形成保形的第二氧化物层。 通过各向异性蚀刻去除部分富Si氧化物层，第二氧化物层和第一氧化物层，以形成由剩余的富Si氧化物层，剩余的第二氧化物层和剩余的第一氧化物层组成的氧化物间隔物。 剩余的第二氧化物层，剩余的第一氧化物层的一部分和富Si氧化物层的一部分被BOE除去。 因此，剩余的第一和富Si氧化物层的一部分形成在沟槽的下表面上，从而减小沟槽纵横比。

公开(公告)号：US06946344B2

公开(公告)日：2005-09-20

申请号：US10620743

申请日：2003-07-16

申请人： Shih-Chung Chou ,  Yi-Nan Chen ,  Tzu-Ching Tsai

发明人： Shih-Chung Chou ,  Yi-Nan Chen ,  Tzu-Ching Tsai

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/8242

CPC分类号： H01L27/10861 ,  H01L27/1087 ,  Y10T29/41

摘要： A method for forming a trench capacitor. A semiconductor substrate with a trench is provided, and a trench capacitor is formed in the trench with a storage node and a node dielectric layer. The top portion of the trench is ion implanted to a predetermined angle to form an ion doped area on a sidewall of the top portion of the trench and a top surface of the trench capacitor. The ion doped area is oxidized to form an oxide layer. A sidewall semiconductor layer is formed on another sidewall using the oxide layer as a mask, and then the oxide layer is removed. A barrier layer is conformally formed on the surface of the trench, and the trench is filled with a conducting layer.

摘要翻译： 一种形成沟槽电容器的方法。 提供具有沟槽的半导体衬底，并且沟槽电容器在沟槽中形成有存储节点和节点电介质层。 将沟槽的顶部离子注入预定角度，以在沟槽顶部的侧壁和沟槽电容器的顶表面上形成离子掺杂区域。 离子掺杂区域被氧化形成氧化物层。 使用氧化物层作为掩模在另一侧壁上形成侧壁半导体层，然后除去氧化物层。 在沟槽的表面上保形地形成阻挡层，并且沟槽填充有导电层。

公开(公告)号：US06929996B2

公开(公告)日：2005-08-16

申请号：US10726434

申请日：2003-12-03

申请人： Chung-Peng Hao ,  Yi-Nan Chen ,  Ming-Cheng Chang

发明人： Chung-Peng Hao ,  Yi-Nan Chen ,  Ming-Cheng Chang

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10838 ,  H01L27/10841

摘要： A double corner rounding process for a partial vertical cell. A first corner rounding process is performed after etching the substrate to form a shallow trench for device isolation. A second corner rounding process is performed after forming shallow trench isolations (STIs) and exposing the corner of the substrate at the active areas in the memory cell array region.

公开(公告)号：US20050124127A1

公开(公告)日：2005-06-09

申请号：US10726500

申请日：2003-12-04

申请人： Tzu-En Ho ,  Chang-Rong Wu ,  Yi-Nan Chen ,  Kuo-Chien Wu

发明人： Tzu-En Ho ,  Chang-Rong Wu ,  Yi-Nan Chen ,  Kuo-Chien Wu

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

摘要： The present invention provides a method for manufacturing a stacked gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a metal layer, a barrier layer, and a tungsten layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.

摘要翻译： 本发明提供一种在半导体器件中制造堆叠栅极结构的方法。 该方法包括以下步骤：在半导体衬底上依次形成栅极电介质层，多晶硅层，金属层，势垒层和钨层，在氮气环境中进行快速热退火（RTA） 在所述钨层上形成氮化硅层，并将所述多层薄膜结构图案化为规定的形态。