公开(公告)号：US06624052B2

公开(公告)日：2003-09-23

申请号：US10200396

申请日：2002-07-22

Applicant: Krishnaswamy Ramkumar ,  Manuj Rathor

Inventor： Krishnaswamy Ramkumar ,  Manuj Rathor

IPC: H01L21425

CPC classification number: H01L29/518 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/324 ,  H01L29/517

Abstract: A method of making a semiconductor structure, includes annealing a structure in a deuterium-containing atmosphere. The structure includes (i) a substrate, (ii) a gate dielectric on the substrate, (iii) a gate on the gate dielectric, (iv) an etch-stop layer on the gate, and (v) an interlayer dielectric on the etch-stop layer.

公开(公告)号：US06555484B1

公开(公告)日：2003-04-29

申请号：US08878728

申请日：1997-06-19

Applicant: Krishnaswamy Ramkumar ,  Hanna Bamnolker

Inventor： Krishnaswamy Ramkumar ,  Hanna Bamnolker

IPC: H01L21265

CPC classification number: H01L21/28185 ,  H01L21/2652 ,  H01L21/2822 ,  Y10S438/911 ,  Y10S438/92 ,  Y10S438/981

Abstract: Two different regions of a semiconductor substrate are implanted with dopants/ions. The implantation may occur though a sacrificial oxide layer disposed over the substrate. Following implantation in one or both regions, the substrate may be annealed and the sacrificial oxide layer removed. An oxide layer is then grown over the implanted regions of the substrate. For some embodiments, the substrate may be implanted with arsenic and/or with phosphorus. Further, the anneal may be performed for approximately 30 to 120 minutes at a temperature between approximately 900° C. and 950° C.

Abstract translation: 用掺杂剂/离子注入半导体衬底的两个不同区域。 注入可以通过设置在衬底上的牺牲氧化层发生。 在一个或两个区域中植入之后，可以对衬底进行退火并去除牺牲氧化物层。 然后在衬底的注入区域上生长氧化物层。 对于一些实施例，衬底可以用砷和/或磷进行注入。 此外，退火可以在约900℃至950℃的温度下进行约30至120分钟。

公开(公告)号：US6033991A

公开(公告)日：2000-03-07

申请号：US939838

申请日：1997-09-29

Applicant: Krishnaswamy Ramkumar ,  Pamela Trammel ,  Sharmin Sadoughi

Inventor： Krishnaswamy Ramkumar ,  Pamela Trammel ,  Sharmin Sadoughi

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L21/302

CPC classification number: H01L21/76202 ,  H01L21/7621 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31662

Abstract: A method of forming a field oxide or an isolation region in a semiconductor die. An oxidation mask layer (over an oxide layer disposed over the substrate) is patterned and subsequently etched, preferably so that the oxidation mask layer may have a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the sidewall of the oxidation mask layer. A field oxide is then grown in the recess using a dry oxidizing atmosphere. The sloped sidewall of the substrate recess effectively moves the face of the exposed substrate away from the edge of the oxidation mask layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and less field oxide thinning. The preferred range of slopes for the substrate sidewall is from approximately 10.degree. to 40.degree. with respect to the oxidation mask layer sidewall.

Abstract translation: 在半导体管芯中形成场氧化物或隔离区域的方法。 对氧化掩模层（位于衬底上方的氧化物层上方）进行构图并随后进行蚀刻，优选地使得氧化掩模层可具有几乎垂直的侧壁。 蚀刻隔离区域中的氧化物层和衬底，以在衬底中形成相对于氧化掩模层的侧壁具有倾斜表面的凹部。 然后使用干燥的氧化气氛将场氧化物生长在凹槽中。 衬底凹槽的倾斜侧壁有效地将暴露的衬底的表面远离氧化掩模层侧壁的边缘移动。 与非倾斜技术相比，氧化似乎从图案化蚀刻的内置偏移开始。 这导致氧化物侵蚀减少和较少的场氧化物稀化。 衬底侧壁的斜率的优选范围相对于氧化掩模层侧壁约为10°至40°。

公开(公告)号：US6004399A

公开(公告)日：1999-12-21

申请号：US784207

申请日：1997-01-15

Applicant: Kaichiu Wong ,  Krishnaswamy Ramkumar ,  Hanna Bamnolker ,  Suraj Puri ,  Rajiv Bhushan ,  David Wong ,  Gary Elmore ,  Raj Mohindra

Inventor： Kaichiu Wong ,  Krishnaswamy Ramkumar ,  Hanna Bamnolker ,  Suraj Puri ,  Rajiv Bhushan ,  David Wong ,  Gary Elmore ,  Raj Mohindra

IPC: B08B3/04 ,  B08B3/10 ,  B08B3/12 ,  H01L21/00 ,  B08B3/08

CPC classification number: H01L21/67057 ,  B08B3/04 ,  B08B3/102 ,  B08B3/12 ,  H01L21/67051 ,  Y10S134/902

Abstract: A method is described for cleaning a semiconductor wafer. The method includes immersing a wafer in a liquid comprising water. The wafer has a front face, a back face, and an edge. The method also includes providing a substantially particle free environment adjacent to the front face and the back face as the liquid is being removed. A step of introducing a carrier gas comprising a cleaning enhancement substance also is included. It is believed that the cleaning enhancement substance dopes any liquid adhered to the front and back faces of the wafer to cause a concentration gradient of the cleaning enhancement substance in the liquid and accelerate removal of the adhered liquid off of the water.

Abstract translation: 描述了一种用于清洁半导体晶片的方法。 该方法包括将晶片浸入包含水的液体中。 晶片具有前表面，后表面和边缘。 该方法还包括当正在除去液体时提供与前表面和背面相邻的基本上无颗粒的环境。 还包括引入包含清洁增强物质的载气的步骤。 相信清洁增强物质会粘附到晶片的正面和背面的任何液体，从而引起液体中清洁增强物质的浓度梯度，并加速从水中除去附着液体。

公开(公告)号：US09431549B2

公开(公告)日：2016-08-30

申请号：US13436875

申请日：2012-03-31

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  B82Y10/00 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/7923 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11578 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/792 ,  H01L29/7926

Abstract: An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

Abstract translation: 描述了非易失性电荷陷阱存储器件的实施例。 在一个实施例中，该装置包括一个通道，该沟道包括覆盖在电连接存储器件的第一扩散区和第二扩散区的衬底上的表面的硅以及与沟道的至少一部分相交并且覆盖的栅极堆，栅极 包括邻接通道的隧道氧化物的堆叠，邻接隧道氧化物的分裂电荷捕获区域和与分离的电荷捕获区域邻接的多层阻挡电介质。 分离电荷捕获区域包括第一电荷捕获层，其包含更接近隧道氧化物的氮化物，以及包含覆盖在第一电荷俘获层上的氮化物的第二电荷俘获层。 多层阻挡电介质至少包括高K电介质层。

公开(公告)号：US08940645B2

公开(公告)日：2015-01-27

申请号：US13539458

申请日：2012-07-01

Applicant: Krishnaswamy Ramkumar ,  Sagy Levy ,  Jeong Byun

Inventor： Krishnaswamy Ramkumar ,  Sagy Levy ,  Jeong Byun

IPC: H01L21/31

CPC classification number: H01L29/7926 ,  B82Y10/00 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28282 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/775

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.

Abstract translation: 描述了制造非易失性电荷陷阱存储器件的方法。 所述方法包括使衬底经受第一氧化工艺以形成覆盖多晶硅沟道的隧道氧化物层，以及在所述隧道氧化物层上形成多层电荷存储层，所述多层电荷存储层包含富氧的第一层，所述第一层包含氮化物，以及 在第一层上包含氮化物的贫氧第二层。 然后对衬底进行第二氧化处理以消耗第二层的一部分并形成覆盖多层电荷存储层的高温氧化物（HTO）层。 第一层的化学计量组成导致其基本上无陷阱，并且第二层的化学计量组成使其陷入致密。 第二氧化过程可以包括使用原位蒸汽发生的等离子体氧化过程或自由基氧化过程。

公开(公告)号：US08859374B1

公开(公告)日：2014-10-14

申请号：US13288919

申请日：2011-11-03

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

IPC: H01L21/336

CPC classification number: H01L29/513 ,  G11C16/0466 ,  G11C16/349 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/28035 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method comprises: (i) forming an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate in at least a first region in which a non-volatile memory transistor is to be formed, the ONO dielectric stack including a multi-layer charge storage layer; (ii) forming an oxide layer on the surface of the substrate in a second region in which a metal oxide semiconductor (MOS) logic transistor is to be formed; and (iii) forming a high work function gate electrode on a surface of the ONO dielectric stack. Other embodiments are also disclosed.

Abstract translation: 提供包括非易失性存储晶体管的半导体器件及其制造方法以改善其性能。 在一个实施例中，该方法包括：（i）在其中将形成非易失性存储晶体管的至少第一区域中，在半导体衬底的表面上形成氧化物 - 氧化物 - 氧化物（ONO）电介质叠层， ONO电介质堆叠包括多层电荷存储层; （ii）在要形成金属氧化物半导体（MOS）逻辑晶体管的第二区域中在所述衬底的表面上形成氧化物层; 和（iii）在ONO电介质叠层的表面上形成高功函数栅电极。 还公开了其他实施例。

公开(公告)号：US08772059B2

公开(公告)日：2014-07-08

申请号：US13430631

申请日：2012-03-26

Applicant: Yu Yang ,  Krishnaswamy Ramkumar

Inventor： Yu Yang ,  Krishnaswamy Ramkumar

IPC: H01L21/66

CPC classification number: H01L29/792 ,  H01L22/14 ,  H01L29/66833

Abstract: Embodiments of structures and methods for determining operating characteristics of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer are described. In one embodiment, the method comprises: forming on a substrate a structure including a nitrided tunneling-layer and a charge-storage-layer overlying the tunneling-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first charge-storage layer, wherein the first charge-storage layer is separated from the second charge-storage layer by a anti-tunneling layer comprising an oxide; depositing a positive charge on the charge-storage-layer and determining a first voltage to establish a first leakage current through the charge-storage-layer and the tunneling-layer; depositing a negative charge on the charge-storage-layer and determining a second voltage to establish a second leakage current through the charge-storage-layer and the tunneling-layer; and determining a differential voltage by calculating a difference between the first and second voltages.

Abstract translation: 描述了用于确定包括电荷存储层和隧穿层的非易失性存储晶体管的操作特性的结构和方法的实施例。 在一个实施例中，该方法包括：在衬底上形成包括氮化隧道层和覆盖隧道层的电荷存储层的结构，该隧穿层包括与隧道层相邻的第一电荷存储层和第二电荷 覆盖在第一电荷存储层上的第一电荷存储层，其中第一电荷存储层通过包含氧化物的反隧道层与第二电荷存储层分离; 在电荷存储层上沉积正电荷并确定第一电压以建立通过电荷存储层和隧道层的第一泄漏电流; 在电荷存储层上沉积负电荷并确定第二电压以建立通过电荷存储层和隧穿层的第二泄漏电流; 以及通过计算所述第一和第二电压之间的差来确定差分电压。

公开(公告)号：US08679927B2

公开(公告)日：2014-03-25

申请号：US12185751

申请日：2008-08-04

Applicant: Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

IPC: H01L29/792

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract translation: 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

公开(公告)号：US08536640B2

公开(公告)日：2013-09-17

申请号：US11904474

申请日：2007-09-26

Applicant: Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William W. Koutny

Inventor： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William W. Koutny

IPC: H01L29/792

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/792

Abstract: A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.