公开(公告)号：US20180090374A1

公开(公告)日：2018-03-29

申请号：US15817554

申请日：2017-11-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Cheng CHI ,  Ruilong XIE

IPC: H01L21/768 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06 ,  H01L27/088 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/45

Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.

公开(公告)号：US20180019337A1

公开(公告)日：2018-01-18

申请号：US15683228

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7827 ,  H01L21/28088 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666

Abstract: An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers, each of the sidewall spacers having vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a temporary hard mask to pattern the SiN hard mask.

公开(公告)号：US20170309522A1

公开(公告)日：2017-10-26

申请号：US15645395

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM ,  Ruilong XIE

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

公开(公告)号：US20170271163A1

公开(公告)日：2017-09-21

申请号：US15072626

申请日：2016-03-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Ruilong XIE ,  Chanro PARK ,  Hoon KIM ,  Kwan-Yong LIM

IPC: H01L21/3065 ,  H01L29/161 ,  H01L27/11 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/161

Abstract: Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.

公开(公告)号：US20170256624A1

公开(公告)日：2017-09-07

申请号：US15060761

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Jinping LIU ,  Ruilong XIE

IPC: H01L29/47 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/40 ,  H01L27/092

CPC classification number: H01L29/47 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/401 ,  H01L29/78

Abstract: Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include providing a substrate having an n-FET region and a p-FET region, each region including a gate between source/drain regions; applying a mask over the n-FET region; selectively amorphizing a surface of the p-FET region source/drain regions while the n-FET region is masked; removing the mask; depositing a titanium-based metal over the n-FET and p-FET region source/drain regions; and microwave annealing.

公开(公告)号：US20170256462A1

公开(公告)日：2017-09-07

申请号：US15373852

申请日：2016-12-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Murat Kerem AKARVARDAR ,  Andreas KNORR

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/3083 ,  H01L21/3105 ,  H01L21/32105 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/7842 ,  H01L29/7849

Abstract: A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.

公开(公告)号：US20170092764A1

公开(公告)日：2017-03-30

申请号：US14867193

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Andre LABONTE ,  Andreas KNORR

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7845 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A three-dimensional transistor includes a semiconductor substrate, a fin coupled to the substrate, the fin including an active region across a top portion thereof, the active region including a source, a drain and a channel region therebetween. The transistor further includes a gate situated above the channel region, and a gate contact situated in the active region, no portion thereof being electrically coupled to the source or drain. The transistor is achieved by removing a portion of the source/drain contact situated beneath the gate contact during fabrication.

公开(公告)号：US20160190322A1

公开(公告)日：2016-06-30

申请号：US14584639

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Qing LIU ,  Ruilong XIE ,  Xiuyu CAI ,  Chun-chen YEH

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/02 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/02181 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract translation: 用于集成电路的大面积电接触具有非平面，倾斜的底部轮廓。 倾斜的底部轮廓提供更大的电接触面积，从而降低接触电阻，同时保持小的接触足迹。 倾斜的底部轮廓可以通过凹陷下面的层来形成，其中底部轮廓可以被制造成具有V形，U形，月牙形或其它轮廓形状，其在竖直方向上至少包括基本上倾斜的部分 。 在一个实施例中，下层是FinFET的外延翅片。 制造低电阻电接触的方法采用用作硬掩模的薄蚀刻停止衬垫。 蚀刻停止衬垫，例如HfO 2，防止在形成接触期间相邻栅极结构的侵蚀。

公开(公告)号：US20160190262A1

公开(公告)日：2016-06-30

申请号：US14676608

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Andreas KNORR

IPC: H01L29/417 ,  H01L29/66 ,  H01L27/088 ,  H01L21/28 ,  H01L21/768 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate and surrounded at a lower portion thereof by a layer of isolation material, gate structure(s) and confined epitaxial material above active regions of the raised structures, the confined epitaxial material having recessed portion(s) therein. Dummy gate structures surrounding a portion of each of the raised structures are initially used, and the confined epitaxial material is created before replacing the dummy gate structures with final gate structures. The structure further includes silicide on upper surfaces of a top portion of the confined epitaxial material, and contacts above the silicide, the contacts including separate contacts electrically coupled to only one area of confined epitaxial material and common contact(s) electrically coupling two adjacent areas of the confined epitaxial material.

Abstract translation: 非平面半导体结构包括半导体衬底，耦合到衬底的多个凸起的半导体结构，并且在其下部被隔离材料层，栅极结构和凸起结构的有源区上方的限定外延材料包围， 该限制外延材料在其中具有凹入部分。 最初使用围绕每个凸起结构的一部分的虚拟门结构，并且在用最终栅极结构替换伪栅极结构之前产生约束的外延材料。 该结构还包括在限制的外延材料的顶部的上表面上的硅化物和硅化物上方的触点，触点包括电耦合到仅限于一部分的限制性外延材料的单独触点和电耦合两个相邻区域 的限制外延材料。

公开(公告)号：US20160181390A1

公开(公告)日：2016-06-23

申请号：US14581857

申请日：2014-12-23

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Xiuyu CAI ,  Chun-chen YEH ,  Ruilong XIE

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417 ,  H01L29/51 ,  H01L21/311 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/45 ,  H01L21/76816 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/5386 ,  H01L29/401 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure is directed to a device and method for reducing the resistance of the middle of the line in a transistor. The transistor has electrical contacts formed above, and electrically connected to, the gate, drain and source. The electrical contact connected to the gate includes a tungsten contact member deposited over the gate, and a copper contact deposited over the tungsten contact member. The electrical contacts connected to the drain and source include tungsten portions deposited over the drain and source regions, and copper contacts deposited over the tungsten portions.

Abstract translation: 本公开涉及一种用于降低晶体管中线的电阻的装置和方法。 晶体管具有形成在栅极，漏极和源极上方并电连接的电触点。 连接到栅极的电触点包括沉积在栅极上的钨接触构件和沉积在钨接触构件上的铜触点。 连接到漏极和源极的电触头包括沉积在漏极和源极区域上的钨部分，以及沉积在钨部分上的铜触点。