公开(公告)号：US10714604B2

公开(公告)日：2020-07-14

申请号：US16017031

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Hubert C. George ,  David J. Michalak ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  Jeanette M. Roberts

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66 ,  H01L29/15 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/12 ,  G06N10/00 ,  B82Y10/00 ,  H01L29/82 ,  H01L29/76 ,  H01L29/423 ,  H01L21/308 ,  H01L29/51 ,  H01L29/43 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L29/16 ,  H01L29/78 ,  H01L29/165

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.

公开(公告)号：US20190044050A1

公开(公告)日：2019-02-07

申请号：US15913799

申请日：2018-03-06

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Kanwaljit Singh ,  Patrick H. Keys ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  James S. Clarke ,  Roza Kotlyar ,  Payam Amin ,  Jeanette M. Roberts

IPC: H01L39/22 ,  H01L39/02 ,  H01L39/04 ,  H01L39/24 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.

公开(公告)号：US20190043974A1

公开(公告)日：2019-02-07

申请号：US15900655

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  James S. Clarke ,  Willy Rachmady

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

公开(公告)号：US20190043955A1

公开(公告)日：2019-02-07

申请号：US16146899

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L29/15 ,  H01L29/66 ,  H01L29/51 ,  H01L29/778 ,  H01L21/02

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a spacer and a capping material, the spacer has a top and a bottom, the bottom of the spacer is between the top of the spacer and the quantum well stack, and the capping material is proximate to the top of the spacer.

公开(公告)号：US20190043953A1

公开(公告)日：2019-02-07

申请号：US16144148

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L29/15 ,  H01L29/66 ,  H01L29/51 ,  H01L23/522

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a multi-spacer between the first gate and the second gate, wherein the multi-spacer includes a first spacer and a second spacer different from the first spacer, and the first spacer is at least partially between the quantum well stack and the second spacer.

公开(公告)号：US20190042968A1

公开(公告)日：2019-02-07

申请号：US16013384

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Lester Lampert ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  James S. Clarke

IPC: G06N99/00 ,  B82Y10/00 ,  H01L27/18 ,  H01L39/22 ,  H03K19/195

Abstract: Embodiments of the present disclosure describe quantum circuit assemblies utilizing triaxial cables to communicate signals to/from quantum circuit components. One assembly includes a cooling apparatus for cooling a quantum circuit component that includes at least one qubit device. The cooling apparatus includes at least one triaxial connector for providing signals to and/or receiving signals from the quantum circuit component using one or more triaxial cables. Other assemblies include quantum circuit components and various electronic components (e.g. attenuators, filters, or amplifiers) for use within the cooling apparatus, adapted to be used with triaxial cables by incorporating triaxial connectors as well.

公开(公告)号：US20190042967A1

公开(公告)日：2019-02-07

申请号：US16011812

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Zachary R. Yoscovits ,  Roman Caudillo ,  Ravi Pillarisetty ,  Hubert C. George ,  Adel A. Elsherbini ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: G06N99/00 ,  H03K19/195 ,  H03K17/92 ,  H01L27/18 ,  B82Y10/00

CPC classification number: G06N10/00 ,  B82Y10/00 ,  G11C11/44 ,  H01L27/18 ,  H01L29/66439 ,  H01L29/66977 ,  H01L39/223 ,  H01L39/2493 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H03K17/92 ,  H03K19/1952

Abstract: Disclosed herein are superconducting qubit devices with Josephson Junctions utilizing resistive switching materials, i.e., resistive Josephson Junctions (RJJs), as well as related methods and quantum circuit assemblies. In some embodiments, an RJJ may include a bottom electrode, a top electrode, and a resistive switching layer (RSL) disposed between the bottom electrode and the top electrode. Using the RSLs in Josephson Junctions of superconducting qubits may allow fine tuning of junction resistance, which is particularly advantageous for optimizing performance of superconducting qubit devices. In addition, RJJs may be fabricated using methods that could be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to approaches for forming conventional Josephson Junctions, such as e.g. double-angle shadow evaporation approach.

公开(公告)号：US12148747B2

公开(公告)日：2024-11-19

申请号：US17033513

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Pratik Koirala ,  Nicole K. Thomas ,  Paul B. Fischer ,  Adel A. Elsherbini ,  Tushar Talukdar ,  Johanna M. Swan ,  Wilfred Gomes ,  Robert S. Chau ,  Beomseok Choi

IPC: H01L27/06 ,  H01L21/765 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US11996411B2

公开(公告)日：2024-05-28

申请号：US16913796

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Anh Phan ,  Nicole K. Thomas ,  Urusa Alaan ,  Seung Hoon Sung ,  Christopher M. Neumann ,  Willy Rachmady ,  Patrick Morrow ,  Hui Jae Yoo ,  Richard E. Schenker ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Ehren Mannebach

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H10B12/00

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/775 ,  H01L29/7851 ,  H10B12/056

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

公开(公告)号：US11942516B2

公开(公告)日：2024-03-26

申请号：US17704906

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  B82Y10/00 ,  G06N10/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/324 ,  H01L23/46 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/43 ,  H01L29/66 ,  H01L29/76 ,  H01L29/778 ,  H01L29/78 ,  H01L29/82

CPC classification number: H01L29/127 ,  B82Y10/00 ,  G06N10/00 ,  H01L21/28158 ,  H01L23/46 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/423 ,  H01L29/42312 ,  H01L29/42364 ,  H01L29/437 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/7831 ,  H01L29/7845 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/324 ,  H01L29/66431 ,  H01L29/778 ,  H01L29/7782 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.