公开(公告)号：US20190393249A1

公开(公告)日：2019-12-26

申请号：US16016387

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Justin WEBER ,  Harold KENNEL ,  Willy RACHMADY ,  Gilbert DEWEY ,  Van H. LE ,  Abhishek SHARMA ,  Patrick MORROW

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8256

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190122985A1

公开(公告)日：2019-04-25

申请号：US16227406

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  Patrick MORROW ,  Kimin JUN

IPC: H01L23/528 ,  H01L23/00 ,  H01L21/768

Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.

公开(公告)号：US20180233409A1

公开(公告)日：2018-08-16

申请号：US15753124

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Il-Seok SON ,  Colin T. CARVER ,  Paul B. FISCHER ,  Patrick MORROW ,  Kimin JUN

IPC: H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L21/306 ,  H01L21/304 ,  H01L21/84 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L21/304 ,  H01L21/30608 ,  H01L21/30625 ,  H01L21/84 ,  H01L21/845 ,  H01L25/0657 ,  H01L27/0886 ,  H01L29/0649

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

公开(公告)号：US20180226492A1

公开(公告)日：2018-08-09

申请号：US15748842

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Paul B. FISCHER ,  Aaron D. LILAK ,  Stephen M. CEA

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642

Abstract: Embodiments of the invention include vertically oriented long channel transistors and methods of forming such transistors. In one embodiment, a method of forming such a transistor may include forming a fin on a semiconductor substrate. Embodiments may also include forming a spacer over an upper portion of the fin and a lower portion of the fin not covered by the spacer may be exposed. Embodiments may also include forming a gate dielectric layer over the exposed portion of the fin. A gate electrode may then be deposited, according to an embodiment. Embodiments may include exposing a top portion of the fin and forming a first source/drain (S/D) region in the top portion of the fin. The second S/D region may be formed by removing the semiconductor substrate to expose a bottom portion of the fin and forming the second S/D region in the bottom portion of the fin.

公开(公告)号：US20180218973A1

公开(公告)日：2018-08-02

申请号：US15747988

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  Mark T. BOHR ,  Patrick MORROW

IPC: H01L23/498 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L23/49827 ,  H01L23/5286 ,  H01L28/00 ,  H01L2224/16227

Abstract: An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.

公开(公告)号：US20170077281A1

公开(公告)日：2017-03-16

申请号：US15122627

申请日：2014-06-13

Applicant: INTEL CORPORATION

Inventor： Kimin JUN ,  Sansaptak DASGUPTA ,  Alejandro X. LEVANDER ,  Patrick MORROW

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/04 ,  H01L29/20 ,  H01L29/66 ,  H01L21/78

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/76254 ,  H01L21/7806 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

Abstract translation: 一种包括在牺牲基板上的极性化合物半导体层上形成阻挡层的方法; 将牺牲衬底耦合到载体衬底以形成其中阻挡层设置在极性化合物半导体层和载体衬底之间的复合结构; 将牺牲衬底与复合结构分离以暴露极化合物半导体层; 以及形成至少一个电路装置。 一种在基板上包括阻挡层的装置; 阻挡层上的晶体管器件; 以及设置在所述阻挡层和所述晶体管器件之间的极性化合物半导体层，所述极性化合物半导体层包含二维电子气。

公开(公告)号：US20240234422A1

公开(公告)日：2024-07-11

申请号：US18614290

申请日：2024-03-22

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Anh PHAN ,  Nicole K. THOMAS ,  Urusa ALAAN ,  Seung Hoon SUNG ,  Christopher M. NEUMANN ,  Willy RACHMADY ,  Patrick MORROW ,  Hui Jae YOO ,  Richard E. SCHENKER ,  Marko RADOSAVLJEVIC ,  Jack T. KAVALIEROS ,  Ehren MANNEBACH

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H10B12/00

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7853 ,  H10B12/056

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

公开(公告)号：US20240186398A1

公开(公告)日：2024-06-06

申请号：US18073213

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Anh PHAN ,  Rishabh MEHANDRU ,  Stephen M. CEA ,  Patrick MORROW ,  Jack T. KAVALIEROS ,  Justin WEBER ,  Salim BERRADA

IPC: H01L29/49 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/4991 ,  H01L21/28123 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

Abstract: Integrated circuit structures having cavity spacers, and methods of fabricating integrated circuit structures having cavity spacers, are described. For example, an integrated circuit structure includes a sub-fin structure over a stack of nanowires. A gate structure is vertically around the stack of nanowires. An internal gate spacer is between vertically adjacent ones of the nanowires and adjacent to the gate structure. A trench contact structure is laterally adjacent to a side of the gate structure. A cavity spacer is laterally between the gate structure and the trench contact structure.

公开(公告)号：US20240154011A1

公开(公告)日：2024-05-09

申请号：US18415251

申请日：2024-01-17

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L27/1266 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/78 ,  H01L29/785 ,  H01L21/2254 ,  H01L29/66545

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20240145557A1

公开(公告)日：2024-05-02

申请号：US18408346

申请日：2024-01-09

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Aaron LILAK ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY

IPC: H01L29/417

CPC classification number: H01L29/41741 ,  H01L29/41775

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.