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    Dynamic random access memory cell with self-aligned strap
    64.
    发明授权
    Dynamic random access memory cell with self-aligned strap 有权
    具有自对准带的动态随机存取存储单元

    公开(公告)号：US09564443B2

    公开(公告)日：2017-02-07

    申请号：US14158956

    申请日：2014-01-20

    Applicant: International Business Machines Corporation

    Inventor： John E. Barth, Jr. ,  Kangguo Cheng ,  Herbert L. Ho ,  Ali Khakifirooz ,  Ravikumar Ramachandran ,  Kern Rim ,  Reinaldo A. Vega

    IPC: H01L27/108 ,  H01L29/417 ,  H01L29/66

    CPC classification number: H01L27/10867 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66181 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/785

    Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.

    Abstract translation: 在形成用于存取晶体管的沟槽电容器以及源极和漏极区域和栅极结构之后，在每个源极区域的第一侧壁上形成介电隔离物，同时物理地暴露每个源极区域的第二侧壁和漏极区域的侧壁。 在去除沟槽顶部电介质部分期间，可以使用每个电介质间隔物作为蚀刻掩模，以形成用于形成带状结构的带状空腔。 可选地，可以进行半导体材料的选择性沉积以形成凸起的源极和漏极区域。 在这种情况下，升高的源极区域仅从第一侧壁生长并且不从第二侧壁生长。 凸起的源极区域可以在形成带状空腔期间用作蚀刻掩模的一部分。 带状结构形成为通过电介质间隔物与相邻的存取晶体管电隔离的自对准结构。

    Strain release in PFET regions
    65.
    发明授权
    Strain release in PFET regions 有权
    应变释放在PFET区域

    公开(公告)号：US09543323B2

    公开(公告)日：2017-01-10

    申请号：US14595316

    申请日：2015-01-13

    Applicant: International Business Machines Corporation

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

    IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L21/3065 ,  H01L29/161 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L27/1211 ,  H01L21/3065 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7849

    Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.

    Abstract translation: 一种制造半导体器件的方法，包括提供绝缘体上的应变硅（SSOI）结构，所述SSOI结构包括设置在衬底上的电介质层，设置在所述电介质层上的硅锗层和设置在所述绝缘体上的应变半导体材料层 直接在硅锗层上，在SSOI结构上形成多个鳍片，在nFET区域中的至少一个鳍片的一部分上形成栅极结构，在pFET区域中的至少一个鳍片的一部分上形成栅极结构 去除pFET区域中的至少一个鳍片的部分上的栅极结构，去除通过去除而暴露的硅锗层，并在pFET区域中的至少一个鳍片的部分上形成新的栅极结构， 新的门结构围绕四面的部分。

    Partially dielectric isolated fin-shaped field effect transistor (FinFET)
    66.
    发明授权
    Partially dielectric isolated fin-shaped field effect transistor (FinFET) 有权
    部分绝缘隔离鳍状场效应晶体管（FinFET）

    公开(公告)号：US09537011B1

    公开(公告)日：2017-01-03

    申请号：US14968816

    申请日：2015-12-14

    Applicant: International Business Machines Corporation

    Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Johnathan E. Faltermeier ,  Edward J. Nowak ,  Kern Rim

    IPC: H01L29/78 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L21/7624 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/30604 ,  H01L21/31105 ,  H01L21/762 ,  H01L21/76202 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7857

    Abstract: One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.

    Abstract translation: 一个实施例提供了一种方法，包括蚀刻鳍状场效应晶体管（FinFET）的鳍以形成减小的鳍，并横向蚀刻所述还原翅片以形成鳍通道，所述翅片通道包括第一翅片通道侧壁和与第 第一鳍通道侧壁。 该方法还包括分别在第一散热片通道侧壁和第二散热片通道侧壁上形成第一薄介电通道和第二薄介电通道。 每个薄介电通道防止翅片通道上的横向外延晶体生长。 该方法还包括蚀刻设置在鳍状通道和FinFET的衬底之间的绝缘体层，以暴露衬底的衬底表面的部分。 在外延沉积之后，在衬底表面的暴露部分上由垂直外延晶体生长形成源外延和漏极外延。

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