公开(公告)号：US07388264B2

公开(公告)日：2008-06-17

申请号：US10948883

申请日：2004-09-24

申请人： Do-Hyung Kim ,  Jin-Ho Kim ,  Byung-Jun Hwang

发明人： Do-Hyung Kim ,  Jin-Ho Kim ,  Byung-Jun Hwang

IPC分类号： H01L29/06

CPC分类号： H01L29/6653 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/823425 ,  H01L29/6659

摘要： A semiconductor device having LDD-type source/drain regions and a method of fabricating the same are provided. The semiconductor device includes at least a pair of gate patterns disposed on a semiconductor substrate and LDD-type source/drain regions disposed at both sides of the gate patterns. The substrate having the gate patterns and the LDD-type source/drain regions is covered with a conformal etch stop layer. The etch stop layer is covered with an interlayer insulating layer. The LDD-type source/drain region is exposed by a contact hole that penetrates the interlayer insulating layer and the etch stop layer. The method of forming the LDD-type source/drain regions and the etch stop layer includes forming low-concentration source/drain regions at both sides of the gate patterns and forming the conformal etch stop layer on the substrate having the low-concentration source/drain regions. Gate spacers are then formed on the sidewalls of the gate patterns. Using the gate patterns and the gate spacers as implantation masks, impurity ions are implanted into the semiconductor substrate to form high-concentration source/drain regions. The spacers are then selectively removed. An interlayer insulating layer is formed on the substrate where the spacers are removed.

摘要翻译： 提供具有LDD型源极/漏极区域的半导体器件及其制造方法。 半导体器件包括设置在半导体衬底上的至少一对栅极图案和设置在栅极图案两侧的LDD型源极/漏极区域。 具有栅极图案和LDD型源极/漏极区域的衬底被保形蚀刻停止层覆盖。 蚀刻停止层被层间绝缘层覆盖。 LDD型源极/漏极区域通过穿透层间绝缘层和蚀刻停止层的接触孔露出。 形成LDD型源极/漏极区域和蚀刻停止层的方法包括在栅极图案的两侧形成低浓度源极/漏极区域，并在具有低浓度源/漏极区域的衬底上形成保形蚀刻停止层， 漏区。 然后在栅极图案的侧壁上形成栅极间隔物。 使用栅极图案和栅极间隔物作为注入掩模，将杂质离子注入到半导体衬底中以形成高浓度源极/漏极区域。 然后选择性地去除间隔物。 在基板上形成层间绝缘层，其中隔离物被去除。

公开(公告)号：US20080001883A1

公开(公告)日：2008-01-03

申请号：US11618664

申请日：2006-12-29

申请人： Jin-Ho Kim ,  Byoung-Ho Lim ,  Bo-Ram Kim

发明人： Jin-Ho Kim ,  Byoung-Ho Lim ,  Bo-Ram Kim

IPC分类号： G09G3/36

CPC分类号： G02F1/134363 ,  G02F2001/134318 ,  G02F2001/13629

摘要： A liquid crystal display (LCD) device includes an array substrate; a gate line formed on the array substrate; a data line formed on the array substrate crossing the gate lines; a thin film transistor formed on the array substrate, the thin film transistor being formed at an intersection between the gate line and the data line; a pixel electrode formed on the array substrate and connected to the thin film transistor; an insulating interlayer formed on an entire surface of the array substrate; a common electrode formed on the insulating interlayer and having a plurality of slits; a metal line formed on the insulating interlayer overlapping the data line and the common electrode; a color filter substrate attached to the array substrate; and a liquid crystal layer formed between the array substrate and the color filter substrate.

摘要翻译： 液晶显示器（LCD）装置包括阵列基板; 形成在阵列基板上的栅极线; 形成在与栅极线交叉的阵列基板上的数据线; 形成在所述阵列基板上的薄膜晶体管，所述薄膜晶体管形成在所述栅极线与所述数据线之间的交点处; 形成在阵列基板上并连接到薄膜晶体管的像素电极; 形成在所述阵列基板的整个表面上的绝缘夹层; 形成在所述绝缘中间层上并具有多个狭缝的公共电极; 形成在绝缘层上的与数据线和公共电极重叠的金属线; 附着到阵列基板的滤色器基板; 以及形成在阵列基板和滤色器基板之间的液晶层。

公开(公告)号：US20070202694A1

公开(公告)日：2007-08-30

申请号：US11589716

申请日：2006-10-31

申请人： Jung-Hun Seo ,  Jin-Gi Hong ,  Yun-Ho Choi ,  Hyun-Chul Kwun ,  Eun-Taeck Lee ,  Jin-Ho Kim

发明人： Jung-Hun Seo ,  Jin-Gi Hong ,  Yun-Ho Choi ,  Hyun-Chul Kwun ,  Eun-Taeck Lee ,  Jin-Ho Kim

IPC分类号： H01L21/44 ,  H01L21/465

CPC分类号： H01L21/76841 ,  C23C16/4405 ,  C23C16/45508 ,  H01L21/28556

摘要： In a method of forming a layer, a titanium layer and a titanium nitride layer may be successively formed on a first wafer. By-products adhered to the inside of a chamber during the formation of the titanium nitride layer may be removed from the chamber. Processes of forming the titanium layer, forming the titanium nitride layer, and removing the by-products may be repeated relative to a second wafer.

摘要翻译： 在形成层的方法中，可以在第一晶片上连续地形成钛层和氮化钛层。 在形成氮化钛层期间附着在室内部的副产物可以从室中除去。 可以相对于第二晶片重复形成钛层，形成氮化钛层和除去副产物的工艺。

公开(公告)号：US20060274248A1

公开(公告)日：2006-12-07

申请号：US11239002

申请日：2005-09-30

申请人： Jin-Ho Kim ,  Sung-O Moon

发明人： Jin-Ho Kim ,  Sung-O Moon

IPC分类号： G02F1/1343

CPC分类号： G02F1/134363 ,  G02F1/133528

摘要： An in-plane switching liquid crystal display device includes a first substrate, a second substrate spaced apart from the first substrate, a liquid crystal layer between the first and second substrates, a first polarizer at an outer surface of the first substrate, the first polarizer including a first polarization film and first inner and outer supporting film at both sides of the first polarization film, the first inner supporting film adjacent to the first substrate and having a retardation within a range of about −10 nm to about +10 nm, and a second polarizer at an outer surface of the second substrate, the second polarizer including a second polarization film and second inner and outer supporting film at both sides of the second polarization film, the second inner supporting film adjacent to the second substrate.

公开(公告)号：US20060237725A1

公开(公告)日：2006-10-26

申请号：US11364773

申请日：2006-02-28

申请人： Jae-Hun Jeong ,  Soon-Moon Jung ,  Hoon Lim ,  Won-Seok Cho ,  Jin-Ho Kim ,  Chang-Min Hong ,  Jong-Hyuk Kim ,  Kun-Ho Kwak

发明人： Jae-Hun Jeong ,  Soon-Moon Jung ,  Hoon Lim ,  Won-Seok Cho ,  Jin-Ho Kim ,  Chang-Min Hong ,  Jong-Hyuk Kim ,  Kun-Ho Kwak

IPC分类号： H01L29/76 ,  H01L29/00

CPC分类号： H01L27/0688 ,  H01L23/485 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.

摘要翻译： 提供具有薄膜晶体管（TFT）的半导体器件及其制造方法。 半导体器件包括设置在半导体衬底上的半导体衬底和下层间绝缘层。 下部半导体本体设置在下部层间绝缘层上或下部层间绝缘层中。 下部TFT包括设置在下部半导体本体中的下部源极区域和下部漏极区域以及下部栅极电极，该下部栅极电极覆盖并交叉配置在下部半导体器件的下部半导体本体的至少两个表面的至少一部分 源极和漏极区域。

公开(公告)号：US20060157848A1

公开(公告)日：2006-07-20

申请号：US11330773

申请日：2006-01-11

申请人： Cheol-Joon Yoo ,  Jin-Ho Kim ,  Hee-Jin Park ,  Tae-Sung Yoon ,  Chan-Suk Lee

发明人： Cheol-Joon Yoo ,  Jin-Ho Kim ,  Hee-Jin Park ,  Tae-Sung Yoon ,  Chan-Suk Lee

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H05K3/3436 ,  H01L23/3128 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In one embodiment, a semiconductor package and a package mounting substrate are joined using a conductive material column such as a solder column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. By forming the insulating protective openings with sufficient depth, each protects the solder column against stress faults and thereby forms more reliable electrical connections and supports high-density electrical connections between the semiconductor package and the package mounting substrate.

摘要翻译： 在一个实施例中，使用诸如焊料柱的导电材料柱将半导体封装和封装安装基板接合。 半导体封装和封装安装衬底中的每一个包括暴露其中的布线层的绝缘保护开口。 焊料柱位于绝缘保护开口内，以电连接布线层。 通过形成具有足够深度的绝缘保护开口，每个保护焊料柱免受应力故障，从而形成更可靠的电连接并且支持半导体封装和封装安装基板之间的高密度电连接。

公开(公告)号：US20050205975A1

公开(公告)日：2005-09-22

申请号：US11077235

申请日：2005-03-11

申请人： In-Ku Kang ,  Seok Goh ,  Jin-Ho Kim ,  Tae-Gyeong Chung ,  Yong-Jae Lee

发明人： In-Ku Kang ,  Seok Goh ,  Jin-Ho Kim ,  Tae-Gyeong Chung ,  Yong-Jae Lee

IPC分类号： H01L25/18 ,  H01L21/301 ,  H01L21/50 ,  H01L21/60 ,  H01L21/78 ,  H01L21/98 ,  H01L23/02 ,  H01L23/12 ,  H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  H01L29/06

CPC分类号： H01L24/32 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49175 ,  H01L2224/4945 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85191 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2224/85186 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/4554

摘要： A variety of non-rectangular IC chips having a stepped or modified periphery or edge profile including one or more recessed or indented peripheral regions are provided for incorporation in modified package configurations, single chip packages and multi-chip assemblies, both stacked and/or planar. In the planar configurations, the recessed regions may be utilized, in cooperation with another appropriately sized IC chip, to increase the packing density of the resulting device. Similarly, in the stacked configuration, the recessed regions may be utilized to provide access to bond pads of lower chips and thereby reduce the need for spacers or peripheral thinning techniques and thereby improve the strength of the resulting assembly and/or reduce the overall height of the stacked structure.

摘要翻译： 提供了具有包括一个或多个凹陷或凹入周边区域的阶梯状或改进的周边或边缘轮廓的各种非矩形IC芯片，用于结合到改进的封装结构，单个芯片封装和多芯片组件中，堆叠和/或平面 。 在平面构造中，可以与另一适当尺寸的IC芯片配合使用凹陷区域，以增加所得器件的封装密度。 类似地，在堆叠构造中，凹陷区域可以用于提供对下部芯片的接合焊盘的访问，从而减少对间隔件或外围变薄技术的需要，从而提高所得组件的强度和/或降低总体高度 堆叠结构。

公开(公告)号：US20050170646A1

公开(公告)日：2005-08-04

申请号：US10772932

申请日：2004-02-04

申请人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

发明人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

IPC分类号： H01L21/44 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

摘要翻译： 在集成电路制造中，使用具有侧向分量的蚀刻。 例如，蚀刻可以是各向同性的。 在层（160）的各向同性蚀刻之前，执行相同层的另一蚀刻。 这种其他蚀刻可以是各向异性的。 该蚀刻攻击通过各向同性蚀刻形成的与特征相邻的层的部分（160×2）。 该部分被各向异性蚀刻完全或部分地去除。 然后，各向同性蚀刻掩模（420）被形成为延伸超过经过各向异性蚀刻的部分的位置的特征。 如果完全去除该部分，则各向同性蚀刻掩模可以完全密封要在该部分侧面上形成的特征，因此不会发生横向蚀刻。 如果该部分仅部分被去除，则横向底切将被阻碍，因为在各向同性蚀刻掩模下的特征的通过将变窄。

公开(公告)号：US06784476B2

公开(公告)日：2004-08-31

申请号：US10039126

申请日：2002-01-03

申请人： Dong-Jun Kim ,  Jin-Ho Kim ,  Yong-Kyu Lee ,  Min-Soo Cho ,  Eui-Youl Ryu

发明人： Dong-Jun Kim ,  Jin-Ho Kim ,  Yong-Kyu Lee ,  Min-Soo Cho ,  Eui-Youl Ryu

IPC分类号： H01L27108

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328

摘要： In a non-volatile semiconductor memory device and a fabrication method thereof, a charge storage layer is formed on a substrate. A control gate layer is formed on the charge storage layer. A gate mask having a spacer-shape is formed on the control gate layer. The charge storage layer and the control gate layer are removed using the gate mask as protection to form a control gate and a charge storage region.

摘要翻译： 在非易失性半导体存储器件及其制造方法中，在基板上形成电荷存储层。 在电荷存储层上形成控制栅极层。 在控制栅极层上形成具有间隔物形状的栅极掩模。 使用栅极掩模去除电荷存储层和控制栅极层作为保护以形成控制栅极和电荷存储区域。

公开(公告)号：US06724661B2

公开(公告)日：2004-04-20

申请号：US10090902

申请日：2002-05-31

申请人： Yong-Kyu Lee ,  Dong-Jun Kim ,  Min-Soo Cho ,  Eui-Youl Ryu ,  Jin-Ho Kim

发明人： Yong-Kyu Lee ,  Dong-Jun Kim ,  Min-Soo Cho ,  Eui-Youl Ryu ,  Jin-Ho Kim

IPC分类号： G11C1604

CPC分类号： G11C16/14

摘要： A method for performing an erase operation in a memory cell. A first voltage and a second voltage are applied to the source and drain regions, respectively, for a predetermined erase time; and the first and second voltages are switched with each other between the source and drain regions at least one time for the erase time. Thereby, hole is easily injected to the source and drain regions and a channel lateral surface, and a uniform and high-speed erase operation is archived.

摘要翻译： 一种在存储单元中执行擦除操作的方法。 分别在源极和漏极区域施加第一电压和第二电压达预定的擦除时间; 并且第一和第二电压在源极和漏极区之间彼此切换至少一次以用于擦除时间。 因此，孔容易地注入到源极和漏极区域以及沟道横向表面，并且存储均匀且高速的擦除操作。