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公开(公告)号：US08735986B2
公开(公告)日：2014-05-27
申请号：US13312442
申请日：2011-12-06
申请人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Robert M. Rassel , Mark E. Stidham
发明人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Robert M. Rassel , Mark E. Stidham
IPC分类号： H01L27/12
CPC分类号： H01L21/76224 , H01L21/26506 , H01L21/823892 , H01L27/04 , H01L27/0623 , H01L27/0635 , H01L27/0802 , H01L27/0811 , H01L27/0928
摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
摘要翻译： 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。
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62.发明授权Backside integration of RF filters for RF front end modules and design structure 有权用于RF前端模块的RF滤波器的背面集成和设计结构公开(公告)号：US09058455B2
公开(公告)日：2015-06-16
申请号：US13354705
申请日：2012-01-20
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： G06F17/50 , H01L21/768 , H01L23/48 , H03H9/64 , H01L23/00 , H01L27/06 , H01L49/02 , H01L23/66 , H01L25/16
CPC分类号： H01L41/293 , G06F17/5063 , G06F17/5068 , H01L21/76898 , H01L23/481 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/24 , H01L25/16 , H01L27/0694 , H01L28/40 , H01L41/0815 , H01L41/25 , H01L2224/03009 , H01L2224/0401 , H01L2224/04105 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/12105 , H01L2224/14181 , H01L2224/16145 , H01L2224/24145 , H01L2225/06548 , H03H9/64
摘要： A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.
摘要翻译： 在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。
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63.发明申请THREE DIMENSIONAL VERTICAL E-FUSE STRUCTURES AND METHODS OF MANUFACTURING THE SAME 失效三维垂直电子熔断器结构及其制造方法公开(公告)号：US20090085152A1
公开(公告)日：2009-04-02
申请号：US11865079
申请日：2007-10-01
申请人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
发明人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
CPC分类号： H01L23/5256 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.
摘要翻译： 本文提供三维垂直电子熔丝结构及其制造方法。 形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。 该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。 垂直e熔丝结构包括第一接触层和第二接触层。 该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。 当施加电流时，导电材料具有增加的电阻。
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公开(公告)号：US09048809B2
公开(公告)日：2015-06-02
申请号：US13342375
申请日：2012-01-03
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
CPC分类号： H03H3/04 , B81B7/008 , B81B7/02 , G06F17/5045 , H01L41/094 , H01L41/0973 , H03H3/08 , H03H9/0542 , H03H9/0547 , H03H9/1064 , H03H9/1092 , H03H9/48 , H03H9/542 , H03H9/6403 , H03H9/6423 , Y10T29/42 , Y10T29/49005 , Y10T29/49126 , Y10T29/49147 , Y10T29/49156
摘要： Switchable and/or tunable filters and methods of manufacture. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam formed above the piezoelectric substrate and at a location in which, upon actuation, the MEMS beam shorts the piezoelectric filter structure by contacting at least one of the plurality of electrodes.
摘要翻译： 可切换和/或可调滤波器和制造方法。 形成滤波器的方法包括形成至少一个包括形成在压电基片上的多个电极的压电滤波器结构。 该方法还包括形成微电子机械结构（MEMS），该微机电结构（MEMS）包括形成在压电基板上方的MEMS光束，并且在致动时，MEMS光束通过使多个或多个之中的至少一个接触而使压电滤波器结构短路的位置 的电极。
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公开(公告)号：US20120098105A1
公开(公告)日：2012-04-26
申请号：US13343422
申请日：2012-01-04
IPC分类号： H01L23/58
CPC分类号： H01L24/05 , H01L23/3114 , H01L23/485 , H01L23/562 , H01L23/585 , H01L24/03 , H01L2224/05553 , H01L2224/0558 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.
摘要翻译： 一种电子封装，其具有位于芯片上的至少一个接合焊盘，用于实现与集成电路的晶圆连接。 电子封装在接合焊盘区域和有源电路区域之间配备有边缘密封，并且包括裂缝停止件，其适于保护布置免受有害水分和组合进入含有 接合垫
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公开(公告)号：US08119456B2
公开(公告)日：2012-02-21
申请号：US12582298
申请日：2009-10-20
CPC分类号： H01L24/05 , H01L23/3114 , H01L23/485 , H01L23/562 , H01L23/585 , H01L24/03 , H01L2224/05553 , H01L2224/0558 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seat between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.
摘要翻译： 一种电子封装，其具有位于芯片上的至少一个接合焊盘，用于实现与集成电路的晶圆连接。 电子封装在接合焊盘区域和有源电路区域之间配备有边缘座，并且包括裂缝停止件，其适于保护布置免受有害水分和组合进入含有 接合垫
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67.发明授权公开(公告)号：US07719118B2
公开(公告)日：2010-05-18
申请号：US11838917
申请日：2007-08-15
CPC分类号： H01L23/3157 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/82 , H01L2224/0401 , H01L2224/16 , H01L2924/10253 , H01L2924/12043 , H01L2924/15311 , H01L2924/00
摘要： A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.
摘要翻译： 形成有可以与衬底隔离或电连接的通孔形成的半导体芯片级封装以及可以隔离或电连接到衬底的具有通孔的半导体芯片级封装的方法。
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公开(公告)号：US07633106B2
公开(公告)日：2009-12-15
申请号：US11164072
申请日：2005-11-09
IPC分类号： H01L31/00
CPC分类号： H01L27/14623 , H01L27/14685
摘要： The present invention provides a light shield for shielding the floating diffusion of a complementary metal-oxide semiconductor (CMOS) imager. In accordance with an embodiment of the present invention, there is provided a pixel sensor cell including: a device region formed on a substrate; and a first layer of material forming a sidewall adjacent to a side of the device region for blocking electromagnetic radiation from the device region.
摘要翻译： 本发明提供一种用于屏蔽互补金属氧化物半导体（CMOS）成像器的浮动扩散的遮光罩。 根据本发明的实施例，提供了一种像素传感器单元，包括：形成在基板上的器件区域; 以及形成与所述器件区域的一侧相邻的侧壁的第一材料层，用于阻挡来自所述器件区域的电磁辐射。
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69.发明申请CHIP SCALE PACKAGE WITH THROUGH-VIAS THAT ARE SELECTIVELY ISOLATED OR CONNECTED TO THE SUBSTRATE 有权通过选择性地分离或连接到基板的通过VI的切片尺寸包公开(公告)号：US20090045502A1
公开(公告)日：2009-02-19
申请号：US11838917
申请日：2007-08-15
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H01L23/3157 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/82 , H01L2224/0401 , H01L2224/16 , H01L2924/10253 , H01L2924/12043 , H01L2924/15311 , H01L2924/00
摘要： A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.
摘要翻译： 形成有可以与衬底隔离或电连接的通孔形成的半导体芯片级封装，以及可以隔离或电连接到衬底的具有通孔的半导体芯片级封装的制造方法。
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公开(公告)号：US20090001427A1
公开(公告)日：2009-01-01
申请号：US11770843
申请日：2007-06-29
IPC分类号： H01L27/148 , H01L31/113 , H01L31/18
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14643
摘要： A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell.
摘要翻译： 像素传感器结构，制造方法和操作方法。 公开了一种缓冲像素单元，其包括用于防止杂散电荷载流子到达暗电流校正像素单元的阻挡区域。 缓冲像素单元位于暗电流校正像素单元附近，并且缓冲像素单元类似于有源像素单元。 因此，围绕暗电流校正像素单元的环境与有源像素单元周围的环境相似。
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