公开(公告)号：US07618891B2

公开(公告)日：2009-11-17

申请号：US11415922

申请日：2006-05-01

申请人： Sunfei Fang ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee T. Mo ,  Balasubramanian Pranatharthiharan ,  Jay W. Strane

发明人： Sunfei Fang ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee T. Mo ,  Balasubramanian Pranatharthiharan ,  Jay W. Strane

IPC分类号： H01L21/00

CPC分类号： H01L21/28518 ,  C23F1/28 ,  C23F1/30 ,  C23F1/44

摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

摘要翻译： 本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。 优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。 更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

公开(公告)号：US07544610B2

公开(公告)日：2009-06-09

申请号：US10935497

申请日：2004-09-07

申请人： Cyril Cabral, Jr. ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

发明人： Cyril Cabral, Jr. ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

IPC分类号： H01L21/477 ,  H01L21/441

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

摘要翻译： 本发明提供一种形成自对准Ni合金硅化物接触的方法。 本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金， 整个半导体结构，其包括至少一个栅极堆叠区域。 包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。 然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。 在绝缘材料如SiO 2和Si 3 N 4中直接接触的金属在退火步骤期间不会转化为金属合金硅化物接触。 然后执行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

公开(公告)号：US20080274611A1

公开(公告)日：2008-11-06

申请号：US12136885

申请日：2008-06-11

申请人： Cyril Cabral ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

发明人： Cyril Cabral ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

摘要翻译： 本发明提供一种形成自对准Ni合金硅化物接触的方法。 本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金， 整个半导体结构，其包括至少一个栅极堆叠区域。 包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。 然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。 与诸如SiO 2和Si 3 N 4 N之类的绝缘材料直接接触的金属在金属合金硅化物接触期间不会转化为金属合金硅化物接触 然后执行退火步骤A选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

公开(公告)号：US20060163083A1

公开(公告)日：2006-07-27

申请号：US11038236

申请日：2005-01-21

申请人： Panayotis Andricacos ,  Donald Canaperi ,  Emanuel Cooper ,  John Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew Mansson ,  Erick Walton ,  Alan West ,  Caliopi Andricacos

发明人： Panayotis Andricacos ,  Donald Canaperi ,  Emanuel Cooper ,  John Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew Mansson ,  Erick Walton ,  Alan West ,  Caliopi Andricacos

IPC分类号： B23H3/00

CPC分类号： C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

摘要： Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

摘要翻译： 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：US06975032B2

公开(公告)日：2005-12-13

申请号：US10319967

申请日：2002-12-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

公开(公告)号：US20050001325A1

公开(公告)日：2005-01-06

申请号：US10611931

申请日：2003-07-03

申请人： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

发明人： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

IPC分类号： H01L21/00 ,  H01L21/288 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76874 ,  H01L21/76883

摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

摘要翻译： 通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。 提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。

公开(公告)号：US06503834B1

公开(公告)日：2003-01-07

申请号：US09677585

申请日：2000-10-03

申请人： Xiaomeng Chen ,  Mahadevaiyer Krishnan ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Soon-Cheon Seo ,  James A. Tornello

发明人： Xiaomeng Chen ,  Mahadevaiyer Krishnan ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Soon-Cheon Seo ,  James A. Tornello

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/288

摘要： The invention provides a process to increase the reliability of BEOL interconnects. The process comprises forming an array of conductors on a dielectric layer on a wafer substrate, polishing the upper surface so that the surfaces of the conductors are substantially co-planar with the upper surface of the dielectric layer, forming an alloy film on the upper surfaces of the conductors, and brush cleaning the upper surfaces of the conductors and the dielectric layer.

摘要翻译： 本发明提供了增加BEOL互连的可靠性的过程。 该方法包括在晶片衬底上的电介质层上形成导体阵列，抛光上表面，使得导体的表面与电介质层的上表面基本上共面，在上表面上形成合金膜 的导体，并刷清洁导体和电介质层的上表面。

公开(公告)号：US06153935A

公开(公告)日：2000-11-28

申请号：US409244

申请日：1999-09-30

申请人： Daniel C. Edelstein ,  Timothy J. Dalton ,  John G. Gaudiello ,  Mahadevaiyer Krishnan ,  Sandra G. Malhotra ,  Maurice McGlashan-Powell ,  Eugene J. O'Sullivan ,  Carlos J. Sambucetti

发明人： Daniel C. Edelstein ,  Timothy J. Dalton ,  John G. Gaudiello ,  Mahadevaiyer Krishnan ,  Sandra G. Malhotra ,  Maurice McGlashan-Powell ,  Eugene J. O'Sullivan ,  Carlos J. Sambucetti

IPC分类号： H01L21/30 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76835

摘要： A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.

摘要翻译： 包含双蚀刻停止/扩散屏障的镶嵌互连。 镶嵌互连的导电材料用导电金属扩散阻挡盖（通常使用无电沉积）和可选地与电介质蚀刻停止层封盖。 还可以存在任选的化学机械抛光 - 停止层。 本发明的不同方法允许不同层的CMP停止，反应离子蚀刻停止和金属扩散阻挡层要求被去耦合。 优选的导电材料是铜。

公开(公告)号：US5635253A

公开(公告)日：1997-06-03

申请号：US487808

申请日：1995-06-07

申请人： Donald F. Canaperi ,  Rangarajan Jagannathan ,  Mahadevaiyer Krishnan

发明人： Donald F. Canaperi ,  Rangarajan Jagannathan ,  Mahadevaiyer Krishnan

IPC分类号： C23C18/31 ,  C23C18/16 ,  C23C18/44 ,  B32B17/10

CPC分类号： C23C18/1617

摘要： A replenishing solution for a cyanide-based electroless gold plating bath. The solution includes a gold(III) halide such as gold chloride, gold bromide, tetrachloroaurate (and its sodium, potassium, and ammonium salts), and tetrabromoaurate (and its sodium, potassium, and ammonium salts). The replenishing solution also may include an alkali (such as potassium hydroxide, sodium hydroxide, and ammonium hydroxide) to maintain the pH of the solution between 8 and 14. Also provided is a method of replenishing a cyanide-based electroless gold plating bath with the solution of the present invention.

摘要翻译： 一种基于氰化物的无电镀金液的补充溶液。 该溶液包括金（III）卤化物如氯化金，溴化金，四氯牛磺酸盐（及其钠盐，钾盐和铵盐）和四溴乙酸盐（及其钠盐，钾盐和铵盐）。 补充溶液还可以包括碱（例如氢氧化钾，氢氧化钠和氢氧化铵），以保持溶液的pH在8和14之间。还提供了一种补充基于氰化物的无电镀金浴的方法， 本发明的溶液。

公开(公告)号：US5102456A

公开(公告)日：1992-04-07

申请号：US618769

申请日：1990-11-27

申请人： Rangarajan Jagannathan ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Gregory P. Wandy

发明人： Rangarajan Jagannathan ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Gregory P. Wandy

IPC分类号： C23C18/40

CPC分类号： C23C18/40 ,  Y10T428/12694 ,  Y10T428/12903 ,  Y10T428/31681

摘要： An electroless copper plating bath uses a series of tetradentate nitrogen ligands. The components of the bath may be substituted without extensive re-optimization of the bath. The Cu-tetra-aza ligand baths operates over a pH range between 7 and 12. Stable bath formulations employing various buffers, reducing agents and ligands have been developed. The process can be used for metal deposition at lower pH and provides the capability to use additive processing for metallization in the presence of polyimide, positive photoresist and other alkali sensitive substrates.

摘要翻译： 化学镀铜浴使用一系列四齿氮配体。 浴的组分可以被代替而没有大量重新优化浴。 Cu-四氮杂配体浴在7和12之间的pH范围内运行。已经开发了使用各种缓冲液，还原剂和配体的稳定浴配方。 该方法可用于较低pH下的金属沉积，并提供在聚酰亚胺，正性光致抗蚀剂和其他碱敏感基材存在下使用添加剂处理进行金属化的能力。