公开(公告)号：US10120128B2

公开(公告)日：2018-11-06

申请号：US15729727

申请日：2017-10-11

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02B6/122 ,  G02B6/136 ,  H01L27/12 ,  G02B6/12 ,  H01L23/48 ,  G02F1/01 ,  H01L23/522

Abstract: A semiconductor device includes: a first substrate; a surface insulating film formed over an upper surface of the first substrate; a BOX layer formed over the surface insulating film; an optical waveguide made of an SOI layer formed on the BOX layer; and a first interlayer insulating film formed over the BOX layer so as to cover the optical waveguide. The semiconductor device further includes: a trench formed in the surface insulating film and the first substrate below the optical waveguide; and a cladding layer made of a buried insulating film buried in the trench. A thickness of the BOX layer is 1 μm or less, and a distance from an interface between the optical waveguide and the BOX layer to a bottom surface of the trench is 2 μm or more.

公开(公告)号：US10115783B2

公开(公告)日：2018-10-30

申请号：US15598475

申请日：2017-05-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba

IPC: H01L31/02 ,  H01L27/08 ,  H01L49/02 ,  G01R31/28 ,  G01R31/303 ,  G01R31/302

Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor chip formation region, a chip internal circuit provided within the semiconductor chip formation region of the semiconductor substrate, a signal transmitting/receiving unit which is provided within the semiconductor chip formation region of the semiconductor substrate, transmits/receives a signal to/from an outside in a non-contact manner by one of electromagnetic induction and capacitive coupling, and transmits/receives a signal to/from the chip internal circuit through electrical connection to the chip internal circuit, and a power receiving inductor which has a diameter provided along an outer edge of the semiconductor chip formation region of the semiconductor substrate so as to surround the chip internal circuit and the signal transmitting/receiving unit, receives a power supply signal from the outside in the non-contact manner, and is electrically connected to the chip internal circuit.

公开(公告)号：US10025048B2

公开(公告)日：2018-07-17

申请号：US15648214

申请日：2017-07-12

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Watanuki ,  Yasutaka Nakashiba

IPC: G02B6/42 ,  G02B6/43 ,  G02B6/12

Abstract: An interposer includes a plurality of identical functional blocks arranged in the x direction, for example, and the functional blocks include a first region mounting a semiconductor chip, a second region mounting a light emitting element chip, a third region mounting a light receiving element chip, and a plurality of silicon waveguides. Then, the second and third regions are arranged between the first region and a first side along the x direction of the interposer. In addition, the plurality of silicon waveguides are arranged between the second region and the first side, and between the third region and the first side, extending from the second region toward the first side and from the third region toward the first side and are not formed between the functional blocks adjacent in the x direction.

公开(公告)号：US20180180827A1

公开(公告)日：2018-06-28

申请号：US15832795

申请日：2017-12-06

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya IIDA ,  Yasutaka Nakashiba

IPC: G02B6/42 ,  H01S5/022 ,  H01S5/042 ,  H01S5/02 ,  G02B6/13 ,  G02B6/12 ,  G02B6/30

CPC classification number: G02B6/4239 ,  G02B6/12004 ,  G02B6/13 ,  G02B6/30 ,  G02B6/4204 ,  G02B6/4232 ,  G02B2006/12061 ,  G02B2006/12121 ,  G02B2006/12123 ,  H01S5/005 ,  H01S5/021 ,  H01S5/02228 ,  H01S5/0224 ,  H01S5/02252 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/024 ,  H01S5/0425

Abstract: A Si photonics device includes: a first semiconductor chip; a second semiconductor chip having a laser diode and mounted on the first semiconductor chip; a third semiconductor chip taking in a laser beam emitted from the laser diode and mounted on the first semiconductor chip; and a resin layer disposed on the first semiconductor chip so as to face the second semiconductor chip. Further, the Si photonics device has: a bump electrode connecting the second semiconductor chip and an upper layer electrode pad provided on the resin layer of the first semiconductor chip; and a bump electrode connecting the first semiconductor chip and the third semiconductor chip, and the second semiconductor chip is mounted on the first semiconductor chip via the resin layer.

公开(公告)号：US09922926B2

公开(公告)日：2018-03-20

申请号：US14638287

申请日：2015-03-04

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba

IPC: G01R15/22 ,  H01L23/522 ,  H01L23/50 ,  H01L23/538 ,  H01L27/04 ,  H01L23/00 ,  H01L23/528 ,  H01L49/02 ,  G01R15/24

CPC classification number: H01L23/5227 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5383 ,  H01L24/48 ,  H01L24/49 ,  H01L27/04 ,  H01L28/10 ,  H01L2224/05553 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit.

公开(公告)号：US09871036B2

公开(公告)日：2018-01-16

申请号：US14209384

申请日：2014-03-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba ,  Yutaka Akiyama

IPC: H01L21/50 ,  H01L23/495 ,  H01L27/12 ,  H01L25/16 ,  H01L27/06 ,  H01L23/522

CPC classification number: H01L27/0688 ,  H01L23/49541 ,  H01L23/5227 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014

Abstract: A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.

公开(公告)号：US09835882B2

公开(公告)日：2017-12-05

申请号：US15152117

申请日：2016-05-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroyuki Kunishima ,  Yasutaka Nakashiba ,  Masaru Wakabayashi ,  Shinichi Watanuki

IPC: G02B6/26 ,  G02F1/025 ,  H01L23/532 ,  G02B6/125 ,  G02B6/132 ,  G02B6/28 ,  G02B6/12

CPC classification number: G02F1/025 ,  G02B6/125 ,  G02B6/132 ,  G02B6/2852 ,  G02B2006/12061 ,  G02B2006/12142 ,  G02B2006/12147 ,  G02F2201/08 ,  H01L23/53214 ,  H01L23/53228 ,  H01L2224/05

Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.

公开(公告)号：US09739964B2

公开(公告)日：2017-08-22

申请号：US15186528

申请日：2016-06-19

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Watanuki ,  Yasutaka Nakashiba

IPC: G02B6/42 ,  G02B6/43 ,  G02B6/12

CPC classification number: G02B6/428 ,  G02B6/43 ,  G02B2006/12061

Abstract: An interposer includes a plurality of identical functional blocks arranged in the x direction, for example, and the functional blocks include a first region mounting a semiconductor chip, a second region mounting a light emitting element chip, a third region mounting a light receiving element chip, and a plurality of silicon waveguides. Then, the second and third regions are arranged between the first region and a first side along the x direction of the interposer. In addition, the plurality of silicon waveguides are arranged between the second region and the first side, and between the third region and the first side, extending from the second region toward the first side and from the third region toward the first side and are not formed between the functional blocks adjacent in the x direction.

公开(公告)号：US08841771B2

公开(公告)日：2014-09-23

申请号：US14075513

申请日：2013-11-08

Applicant: Renesas Electronics Corporation

Inventor： Masayuki Furumiya ,  Yasutaka Nakashiba ,  Akira Tanabe

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8238

CPC classification number: H01L23/481 ,  H01L21/823871 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/5286 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern.

Abstract translation: 具有晶体管区域的半导体器件具有形成在位于信号线下方并位于晶体管区域之上的多层互连结构内的第一导体图案。 第一导体图案耦合到地或电源并与晶体管区重叠。 信号线与第一导体图案重叠。

公开(公告)号：US20140246743A1

公开(公告)日：2014-09-04

申请号：US14279603

申请日：2014-05-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba

IPC: H01L49/02

CPC classification number: H01L28/10 ,  G01R31/2886 ,  G01R31/3025 ,  G01R31/303 ,  H01L23/48 ,  H01L23/645 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate, an internal circuit including a plurality of transistors provided over the substrate, an insulating film provided over the substrate, a bonding pad provided over the insulating film, an inductor being formed in the insulating film, the inductor carrying out a signal transmission/reception to/from an external device in a non-contact manner by an electromagnetic induction and being electrically coupled to the internal circuit. The inductor includes a first conducting layer, and the bonding pad includes a second conducting layer. The first conducting layer includes a lower level layer than the second conducting layer in a thickness direction of the substrate. Ina plan view, the inductor includes a first portion overlapping the bonding pad and a second portion not overlapping the bonding pad.

Abstract translation: 半导体器件包括衬底，包括设置在衬底上的多个晶体管的内部电路，设置在衬底上的绝缘膜，设置在绝缘膜上的接合焊盘，形成在绝缘膜中的电感器，电感器执行 通过电磁感应以非接触方式向外部设备发送/接收信号，并且电耦合到内部电路。 电感器包括第一导电层，并且焊盘包括第二导电层。 第一导电层在衬底的厚度方向上包括比第二导电层低的层。 在俯视图中，电感器包括与接合焊盘重叠的第一部分和不与接合焊盘重叠的第二部分。