公开(公告)号：US12009305B2

公开(公告)日：2024-06-11

申请号：US18302101

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/532 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53242 ,  H01L21/3215 ,  H01L21/76883 ,  H01L23/5226

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

公开(公告)号：US20240096677A1

公开(公告)日：2024-03-21

申请号：US18521314

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/68 ,  G06T1/00 ,  G06T7/00 ,  G06T7/73 ,  H01L23/544

CPC classification number: H01L21/681 ,  G06T1/0014 ,  G06T7/0004 ,  G06T7/73 ,  H01L23/544 ,  G06T2207/30148 ,  H01L2223/54493

Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.

公开(公告)号：US11935793B2

公开(公告)日：2024-03-19

申请号：US16887154

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Tien-Shun Chang ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/223 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/823418 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/26586 ,  H01L21/823425

Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.

公开(公告)号：US11901218B2

公开(公告)日：2024-02-13

申请号：US17715261

申请日：2022-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

公开(公告)号：US11862694B2

公开(公告)日：2024-01-02

申请号：US17223293

申请日：2021-04-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Shih-Hsiang Chiu ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78 ,  H01L21/311 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/40 ,  H01L21/3115

CPC classification number: H01L29/41791 ,  H01L21/28568 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

公开(公告)号：US11854853B2

公开(公告)日：2023-12-26

申请号：US17199980

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/68 ,  H01L23/544 ,  G06T7/73 ,  G06T1/00 ,  G06T7/00

CPC classification number: H01L21/681 ,  G06T1/0014 ,  G06T7/0004 ,  G06T7/73 ,  H01L23/544 ,  G06T2207/30148 ,  H01L2223/54493

Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.

公开(公告)号：US20230411474A1

公开(公告)日：2023-12-21

申请号：US18366369

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Shih-Hsiang Chiu ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78 ,  H01L21/311 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/40 ,  H01L21/3115

CPC classification number: H01L29/41791 ,  H01L27/0924 ,  H01L29/45 ,  H01L29/7851 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/28568 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/401 ,  H01L29/66795

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

公开(公告)号：US20230411156A1

公开(公告)日：2023-12-21

申请号：US18362463

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Chun-Yen Chang ,  Chih-Kai Yang ,  Yu-Tien Shen ,  Ya Hui Chang

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0274 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/31144

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

公开(公告)号：US20230386847A1

公开(公告)日：2023-11-30

申请号：US18358609

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa Luan ,  Yi-Fan Chen ,  Chun-Yen Peng ,  Cheng-Po Chau ,  Wen-Yu Ku ,  Huicheng Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L29/51 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L21/28185 ,  H01L21/28176 ,  H01L29/785 ,  H01L29/66477 ,  H01L21/2254 ,  H01L29/517 ,  H01L29/66545 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/513 ,  H01L29/41791

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

公开(公告)号：US20230317519A1

公开(公告)日：2023-10-05

申请号：US18330466

申请日：2023-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76883 ,  H01L21/76825 ,  H01L23/5226 ,  H01L29/66795

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.