公开(公告)号：US09812426B1

公开(公告)日：2017-11-07

申请号：US15257920

申请日：2016-09-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Te Wang ,  Cheng-Hsien Hsieh ,  Hsien-Wei Chen ,  Li-Han Hsu ,  Tzu-Shiun Sheu ,  Wei-Cheng Wu ,  Yan-Fu Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/13 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/02166 ,  H01L2224/02206 ,  H01L2224/0221 ,  H01L2224/113 ,  H01L2224/13018 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586

Abstract: A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.

公开(公告)号：US09673205B2

公开(公告)日：2017-06-06

申请号：US14834423

申请日：2015-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Ming Wu ,  Wei-Cheng Wu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Harry Hak-Lay Chuang

IPC: H01L27/115 ,  H01L27/11521 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11521 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/32137 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53271 ,  H01L23/5329 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

公开(公告)号：US09659620B2

公开(公告)日：2017-05-23

申请号：US14670241

申请日：2015-03-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Huei Chen ,  Hung-Jen Liao ,  Chih-Yu Lin ,  Jonathan Tsung-Yung Chang ,  Wei-Cheng Wu

IPC: G11C11/34 ,  G11C7/00 ,  G11C8/00 ,  G11C8/08 ,  G11C11/418

CPC classification number: G11C8/08 ,  G11C11/418

Abstract: An electronic device is disclosed that includes memory cells, a word line, a selection unit and a self-boosted driver. The memory cells are configured to store data. The word line is coupled to the memory cells. The selection unit is disposed at a first terminal of the word line, and is configured to transmit a selection signal to activate the word line according to one of a read command and a write command. The self-boosted driver is disposed at a second terminal of the word line, and is configured to pull up a voltage level of the word line according to a voltage level of the word line and a control signal.

公开(公告)号：US09082630B2

公开(公告)日：2015-07-14

申请号：US14075617

申请日：2013-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry Hak-Lay Chuang ,  Wei-Cheng Wu

IPC: H01L29/00 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/105

CPC classification number: H01L27/0617 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided in the present disclosure. The semiconductor device includes a substrate including a first area and a second area divided by a shallow trench isolation (STI) area, a first dummy structure on the STI area, a second dummy structure located on the STI area, a first semiconductor structure on the first area, and a second semiconductor structure on the second area of the substrate including a high-k dielectric layer and a metal gate layer over the high-k dielectric layer. The method for fabricating the semiconductor device is a high-k dielectric first, high-k metal gate last procedure.

Abstract translation: 在本公开中提供半导体器件和制造半导体器件的方法。 该半导体器件包括：衬底，其包括第一区域和由浅沟槽隔离区域（STI）区域划分的第二区域; STI区域上的第一虚拟结构;位于STI区域上的第二虚拟结构;位于STI区域上的第一半导体结构; 第一区域和第二半导体结构，所述第二半导体结构在所述基板的所述第二区域上包括在所述高k电介质层上方的高k电介质层和金属栅极层。 制造半导体器件的方法是高k电介质第一，高k金属栅最后程序。

公开(公告)号：US20240421111A1

公开(公告)日：2024-12-19

申请号：US18506747

申请日：2023-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Pin Chang ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L23/00

Abstract: A package device includes a top die having a top interconnect structure on a first surface of a transistor layer and a bottom interconnect structure on a second surface of the transistor layer. One of the top interconnect structure or the bottom interconnect structure is direct bonded onto a bottom die. The bottom interconnect structure includes a power rail which directly contacts transistor contacts that are directly contacting a transistor structure in the transistor layer.

公开(公告)号：US20240266298A1

公开(公告)日：2024-08-08

申请号：US18616427

申请日：2024-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Fu Lin ,  Chen-Hua Yu ,  Meng-Tsan Lee ,  Wei-Cheng Wu ,  Hsien-Wei Chen

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/5286 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L25/105 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/562 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/17181 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73101 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A fan-out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

公开(公告)号：US11923427B2

公开(公告)日：2024-03-05

申请号：US17185915

申请日：2021-02-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Wei-Cheng Wu ,  Te-Hsin Chiu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L29/42368 ,  H01L21/02244 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.

公开(公告)号：US11612057B2

公开(公告)日：2023-03-21

申请号：US17815373

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Hsieh ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Li-Han Hsu ,  Wei-Cheng Wu

IPC: H01L23/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

公开(公告)号：US11233156B2

公开(公告)日：2022-01-25

申请号：US16743926

申请日：2020-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng Wu ,  Chih-Ren Hsieh

IPC: H01L21/26 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/788 ,  H01L29/423 ,  H01L29/45 ,  H01L21/285 ,  H01L21/265

Abstract: A memory device includes a semiconductor fin, a floating gate, a control gate, a source region, an erase gate, and a select gate. The floating gate is above and conformal to the semiconductor fin. The control gate is above the floating gate. The source region is in the semiconductor fin. The erase gate is above the source region and adjacent the control gate. The select gate is above the semiconductor fin. The control gate is between the erase gate and the select gate.

公开(公告)号：US11211388B2

公开(公告)日：2021-12-28

申请号：US16022702

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei-Cheng Wu ,  Li-Feng Teng ,  Chien-Hung Chang

IPC: H01L27/112 ,  H01L29/06 ,  H01L23/00 ,  H01L21/765 ,  H01L29/40 ,  H01L29/66 ,  H01L27/11534 ,  H01L21/762 ,  H01L27/11524 ,  H01L27/11546 ,  H01L21/28

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.