公开(公告)号：US20050087872A1

公开(公告)日：2005-04-28

申请号：US10766739

申请日：2004-01-29

申请人： Kazuhide Abe

发明人： Kazuhide Abe

IPC分类号： H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The wiring structure of a semiconductor device of the invention enhances the dielectric strength of the wirings and reduces the capacitance across the wirings, by preventing a diffusion of the wiring material. The wiring structure includes a first insulating film, plural wiring films, plural barrier films, and plural cap films. The first insulating film has plural grooves formed thereon, and has an interface in the horizontal direction between the adjoining grooves. The wiring films are formed to protrude from the interface each by the grooves of the first insulating film. The barrier films are formed on the bottoms of the wiring films, and also on side faces of the wiring films to a height exceeding the interface. The cap films are formed at least on the upper faces of the wiring films, and are separated each by the grooves.

摘要翻译： 本发明的半导体器件的布线结构通过防止布线材料的扩散，增强布线的介电强度并降低布线两端的电容。 布线结构包括第一绝缘膜，多个布线膜，多个阻挡膜和多个盖膜。 第一绝缘膜具有形成在其上的多个槽，并且在相邻的槽之间具有在水平方向上的界面。 布线膜形成为从第一绝缘膜的沟槽各自的界面突出。 阻挡膜形成在布线膜的底部以及布线膜的侧面上，达到超过界面的高度。 盖膜至少形成在布线膜的上表面上，并由沟槽分开。

公开(公告)号：US06767812B2

公开(公告)日：2004-07-27

申请号：US09984383

申请日：2001-10-30

申请人： Kazuhide Abe ,  Yusuke Harada

发明人： Kazuhide Abe ,  Yusuke Harada

IPC分类号： H01L2128

CPC分类号： C23C16/0272 ,  C23C16/14

摘要： Before deposition of a CVD titanium film on a cobalt silicide layer, an element which reacts with titanium is provided in the cobalt silicide layer in advance. Thereafter, the CVD titanium film is deposited on the cobalt silicide using a titanium tetrachloride gas.

摘要翻译： 在将CVD钛膜沉积在硅化钴层上之前，预先在钴硅化物层中提供与钛反应的元素。 此后，使用四氯化钛气体将CVD钛膜沉积在硅化钴上。

公开(公告)号：US09041182B2

公开(公告)日：2015-05-26

申请号：US13688823

申请日：2012-11-29

申请人： Toshihiko Nagano ,  Kazuhide Abe ,  Hiroshi Yamada ,  Kazuhiko Itaya ,  Taihei Nakada

发明人： Toshihiko Nagano ,  Kazuhide Abe ,  Hiroshi Yamada ,  Kazuhiko Itaya ,  Taihei Nakada

IPC分类号： H01L23/48 ,  H01L21/78 ,  H01L23/055 ,  H01L23/10 ,  H01L23/00 ,  H01L23/66

CPC分类号： H01L23/48 ,  H01L21/78 ,  H01L23/055 ,  H01L23/10 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/13007 ,  H01L2224/13111 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14181 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81205 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/81986 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/15788 ,  H01L2924/16153 ,  H01L2224/81 ,  H01L2924/01079 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.

摘要翻译： 根据实施例的半导体封装包括：半导体芯片，其前表面包括前电极，背面具有背电极; 在半导体芯片和前侧盖部分之间的部分中包括气隙的前侧盖部分和前侧穿透电极，并且被定位成面向半导体芯片的前表面; 与第一帽部接合以密封半导体芯片的背面盖部分至少在半导体芯片和背面侧帽部分之间的部分和背面贯通电极之间包括气隙，并且位于 面对半导体芯片的背面; 电连接前电极和前侧穿透电极的前侧连接部; 以及将背面电极和背面贯通电极电连接的背面侧连接部。

公开(公告)号：US08419497B2

公开(公告)日：2013-04-16

申请号：US12923949

申请日：2010-10-15

申请人： Isao Takasu ,  Yuko Nomura ,  Tsuyoshi Hioki ,  Isao Amemiya ,  Kazuhide Abe

发明人： Isao Takasu ,  Yuko Nomura ,  Tsuyoshi Hioki ,  Isao Amemiya ,  Kazuhide Abe

IPC分类号： H01J9/00

CPC分类号： H01L33/54 ,  H01L33/46 ,  H01L33/507 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2933/0041 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of manufacturing a light emitting device. The method includes: mounting a light emitting chip on a substrate; forming a transparent resin portion and a phosphor layer by using a liquid droplet discharging apparatus, the transparent resin portion being formed in a shape of a dome and covering the light emitting chip to fill an exterior thereof on the substrate, a phosphor layer containing phosphor and being formed on an exterior of the transparent resin portion close to at least a top side thereof; and forming a reflecting layer at a position exterior of the transparent resin portion and the phosphor layer close to the substrate.

摘要翻译： 一种制造发光器件的方法。 该方法包括：将发光芯片安装在基板上; 通过使用液滴喷射装置形成透明树脂部分和荧光体层，所述透明树脂部分形成为圆顶形状并且覆盖所述发光芯片以将其外部填充在所述基板上，所述荧光体层包含磷光体和 形成在透明树脂部分的至少其顶侧附近的外部; 并且在透明树脂部分的外部和靠近基板的荧光体层的位置处形成反射层。

公开(公告)号：US20120228755A1

公开(公告)日：2012-09-13

申请号：US13235386

申请日：2011-09-18

申请人： Toshihiko NAGANO ,  Hiroshi Yamada ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Taihei Nakada

发明人： Toshihiko NAGANO ,  Hiroshi Yamada ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Taihei Nakada

IPC分类号： H01L23/053 ,  H01L21/56

CPC分类号： H01L23/04 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00

摘要： A semiconductor module includes a high frequency chip, an insulating cap, a through electrode, interconnections, and an insulating layer. The insulating cap forms a hollow with the chip to cover the chip. The through electrode passes through a first plane of the cap and a second plane of the cap, the first plane facing the chip, the second plane being on a side opposite to the first plane. The interconnections are provided on the cap and connected to the through electrode. The insulating layer is provided on the cap and fills a portion between the interconnections therewith.

摘要翻译： 半导体模块包括高频芯片，绝缘帽，通孔，互连和绝缘层。 绝缘盖形成具有芯片的中空以覆盖芯片。 所述贯通电极通过所述盖的第一平面和所述盖的第二平面，所述第一平面面向所述芯片，所述第二平面位于与所述第一平面相对的一侧。 互连设置在盖上并连接到通孔。 绝缘层设置在盖上并填充与其互连之间的部分。

公开(公告)号：US07619470B2

公开(公告)日：2009-11-17

申请号：US11687770

申请日：2007-03-19

申请人： Kazuhide Abe ,  Tadahiro Sasaki ,  Kazuhiko Itaya ,  Hideyuki Funaki

发明人： Kazuhide Abe ,  Tadahiro Sasaki ,  Kazuhiko Itaya ,  Hideyuki Funaki

IPC分类号： H03F3/217

CPC分类号： H03F3/2176 ,  H03F1/02 ,  H03F3/245 ,  H03F2200/366 ,  H03F2200/391 ,  H03F2203/21178 ,  H03G1/0088

摘要： A power amplifier includes: a plurality of field effect transistors connected in parallel and each having a first and second ends, the first end being connected to ground; an amplifying unit which includes at least one of an inductor, a capacitor and a band pass filter and has a third and fourth ends, the third end being connected to the second ends of the field effect transistors, and the fourth end outputting an amplified output signal; and an amplitude controller which sends control signals respectively to gates of the field effect transistors to turn on or off the field effect transistors based on an address signal for performing selection on the field effect transistors and a clock signal. Channel widths of the field effect transistors are different from each other.

摘要翻译： 功率放大器包括：多个并联连接的场效应晶体管，每个具有第一和第二端，所述第一端连接到地; 放大单元，其包括电感器，电容器和带通滤波器中的至少一个，并具有第三和第四端，第三端连接到场效应晶体管的第二端，第四端输出放大的输出 信号; 以及幅度控制器，其基于用于对场效应晶体管进行选择的地址信号和时钟信号，分别向场效应晶体管的栅极发送控制信号以导通或关闭场效应晶体管。 场效应晶体管的沟道宽度彼此不同。

公开(公告)号：US20090134430A1

公开(公告)日：2009-05-28

申请号：US12276787

申请日：2008-11-24

申请人： Kazuhide Abe ,  Tadahiro Sasaki ,  Kazuhiko Itaya

发明人： Kazuhide Abe ,  Tadahiro Sasaki ,  Kazuhiko Itaya

IPC分类号： H01L27/105

CPC分类号： H01L27/088 ,  H01L23/4824 ,  H01L27/0207 ,  H01L27/105 ,  H01L29/1033 ,  H01L29/41758 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a substrate including an element region having a polygonal shape defined by a plurality of edges, and an isolation region surrounding the element region, and a plurality of gate electrodes provided on the substrate, crossing the element region, arranged in parallel with each other, and electrically connected with each other, wherein at least one of the edges does not cross any of the gate electrodes, and is not parallel to the gate electrodes.

摘要翻译： 半导体器件包括：衬底，其包括具有由多个边缘限定的多边形形状的元件区域和围绕该元件区域的隔离区域;以及多个栅电极，设置在该衬底上，与该元件区域交叉，与该 彼此电连接，其中至少一个边缘不与任何栅电极交叉，并且不平行于栅电极。

公开(公告)号：US07508268B2

公开(公告)日：2009-03-24

申请号：US11857737

申请日：2007-09-19

申请人： Tadahiro Sasaki ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Hideyuki Funaki

发明人： Tadahiro Sasaki ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Hideyuki Funaki

IPC分类号： H03F3/68

CPC分类号： H03F3/604 ,  H01L21/823425 ,  H01L27/088 ,  H03F1/3205 ,  H03F3/16 ,  H03F3/607 ,  H03F3/72 ,  H03F2200/108 ,  H03F2200/451 ,  H03F2200/468 ,  H03F2200/543 ,  H03F2200/78 ,  H03F2203/7236

摘要： A power amplifier includes: a first multi-finger FET formed on a semiconductor substrate; a second multi-finger FET formed on the semiconductor substrate; a first temperature detector which detects a channel temperature of the first FET; a second temperature detector which detects a channel temperature of the second FET; a third temperature detector which detects a temperature of the semiconductor substrate; a first detection circuit detecting a difference between an output of the first temperature detector and an output of the third temperature detector and converting the difference to thermoelectromotive force; a second detection circuit detecting a difference between an output of the second temperature detector and the output of the third temperature detector and converting the difference to thermoelectromotive force; and a comparator comparing outputs of the first and second detection circuits with each other to turn on one of the first and second switches and turn off the other.

摘要翻译： 功率放大器包括：形成在半导体衬底上的第一多指FET; 形成在半导体衬底上的第二多指FET; 第一温度检测器，其检测第一FET的通道温度; 第二温度检测器，其检测第二FET的通道温度; 第三温度检测器，其检测半导体衬底的温度; 第一检测电路，检测第一温度检测器的输出和第三温度检测器的输出之间的差异，并将差值转换为热电动势; 第二检测电路，检测第二温度检测器的输出与第三温度检测器的输出之间的差异，并将差值转换为热电动势; 以及比较器，将第一和第二检测电路的输出彼此进行比较，以打开第一和第二开关中的一个并且关闭另一个。

公开(公告)号：US07144812B2

公开(公告)日：2006-12-05

申请号：US10748254

申请日：2003-12-31

申请人： Kazuhide Abe

发明人： Kazuhide Abe

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76838 ,  H01L21/76858 ,  H01L21/76867

摘要： Cu is nitrided to form a nitride of Cu 5 on a Cu wiring layer 1. A diffusion base material layer 6 used as a diffusion source and a barrier metal layer 7, which are interdiffused with Cu, are formed on the nitride of Cu 5. With heat treatment, the Cu wiring layer 1 and the diffusion base material layer 6 are interdiffused to form an alloy layer of Cu 8 between the Cu wiring layer 1 and the barrier metal layer 7.

摘要翻译： Cu在Cu布线层1上被氮化以形成Cu 5的氮化物。 在Cu 5的氮化物上形成有用作扩散源的扩散基材层6和与Cu相互扩散的阻挡金属层7。 通过热处理，Cu配线层1和扩散基材层6相互扩散，在Cu配线层1和阻挡金属层7之间形成Cu 8的合金层。

公开(公告)号：US20060065917A1

公开(公告)日：2006-03-30

申请号：US11228188

申请日：2005-09-19

申请人： Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

发明人： Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

IPC分类号： H01L29/94

CPC分类号： H01L27/11502 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/11507

摘要： A hybrid memory device includes a plurality of regions including a memory cell array region upon which are formed a plurality of memory cells and a logic circuit region upon which is formed a logic circuit device, and is provided with a liner oxide layer formed on a region covering the logic circuit region except the memory cell array region and a cover layer formed on the liner oxide layer while extending to the memory cell array region.

摘要翻译： 一种混合存储器件包括多个区域，包括形成有多个存储单元的存储单元阵列区域和形成逻辑电路器件的逻辑电路区域，并且在其上形成有衬底氧化物层 覆盖除了存储单元阵列区域之外的逻辑电路区域和形成在衬垫氧化物层上的覆盖层，同时延伸到存储单元阵列区域。