公开(公告)号：US09431991B2

公开(公告)日：2016-08-30

申请号：US14569788

申请日：2014-12-15

申请人： Wistron Corporation

发明人： Sheng-Lun Chiou ,  Yin-Yu Chen

IPC分类号： H03H7/01 ,  H01P1/203 ,  H03H7/42 ,  H01P3/08 ,  H01P1/20 ,  H05K1/00

CPC分类号： H03H7/427 ,  H01P1/20 ,  H01P1/203 ,  H01P1/20345 ,  H01P1/20381 ,  H01P3/082 ,  H05K1/00 ,  H05K1/0227 ,  H05K1/0245 ,  H05K2201/09263

摘要： A common mode filter includes a ground element, a transmission line pair and an extension element, which are disposed in first to third signal layers of a circuit board. The ground element includes a ground portion and a first ground line electrically connected with each other. The first ground line is disposed in a slot of the ground portion, and extends from a bottom portion to an opening of the slot. An orthogonal projection of the transmission line pair on the first signal layer is partially overlapped with an orthogonal projection of the ground portion on the first signal layer. The orthogonal projection of the transmission line pair on the first signal layer is not overlapped with an orthogonal projection of the first ground line on the first signal layer. The extension element is electrically connected to the first ground line through at least one conductive via.

摘要翻译： 共模滤波器包括配置在电路板的第一至第三信号层中的接地元件，传输线对和延伸元件。 接地元件包括彼此电连接的接地部分和第一接地线。 第一接地线设置在接地部分的槽中，并且从底部延伸到槽的开口。 传输线对在第一信号层上的正交投影部分地与第一信号层上接地部分的正交投影重叠。 传输线对在第一信号层上的正交投影不与第一接地线在第一信号层上的正交投影重叠。 延伸元件通过至少一个导电通孔电连接到第一接地线。

公开(公告)号：US20160197389A1

公开(公告)日：2016-07-07

申请号：US14878688

申请日：2015-10-08

申请人： SK hynix Inc.

发明人： Kuo Ying HUNG

IPC分类号： H03H1/00 ,  H05K1/18 ,  H05K9/00 ,  H01P1/20 ,  H05K1/02

CPC分类号： H05K9/0081 ,  H01P1/2039 ,  H01P3/026 ,  H05K1/0227 ,  H05K1/0245

摘要： An electromagnetic interference suppressing structure including a multi-layered substrate; a differential pair including first and second signal lines which are disposed on a first layer of the multi-layered substrate; and two grounding recess structures disposed symmetrically in a second layer of the multi-layered substrate which is positioned under the first layer, and on both sides, respectively, of the differential pair, wherein no electrical coupling element extends across a region lying directly under the differential pair, between the two grounding recess structures.

摘要翻译： 包括多层基板的电磁干扰抑制结构; 差分对，包括设置在所述多层基板的第一层上的第一和第二信号线; 以及两个接地凹陷结构，其对称地设置在位于第一层下方的多层基板的第二层中，并且分别位于差分对的两侧，其中没有电耦合元件延伸穿过位于 两个接地凹槽结构之间的差动对。

公开(公告)号：US20160172734A1

公开(公告)日：2016-06-16

申请号：US14570791

申请日：2014-12-15

申请人： Intel Corporation

发明人： Min Wang ,  Russell N. Shryock

IPC分类号： H01P3/08

CPC分类号： H05K1/0245 ,  H01P3/026 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09636

摘要： An interconnect topology is disclosed that includes a plurality of interconnections, each of which is coupled together using a via, where at least two of the vias are staggered with respect to each other. In one embodiment, the interconnect topology comprises a substrate, multiple signal traces routed through the substrate on multiple layers, and a plurality of vias, where each via couples a pair of the signal traces to form an interconnection between different ones of the multiple layers, and where a pair of vias comprise a first via to carry a positive differential signal via and a second via to carry a negative differential signal that are coupled to signal traces to form a differential signal pair. The differential first and second vias are staggered with respect to each other.

摘要翻译： 公开了一种互连拓扑，其包括多个互连，每个互连使用通孔耦合在一起，其中至少两个通孔相对于彼此交错。 在一个实施例中，互连拓扑包括衬底，通过多层上的衬底布线的多个信号迹线以及多个通孔，其中每个通孔耦合一对信号迹线以形成多个不同层之间的互连， 并且其中一对通孔包括第一通孔以承载正差分信号通路和第二通孔，以携带耦合到信号迹线的负差分信号以形成差分信号对。 差分第一和第二通孔相对于彼此交错。

公开(公告)号：US09357632B1

公开(公告)日：2016-05-31

申请号：US13866289

申请日：2013-04-19

申请人： Juniper Networks, Inc.

发明人： K. Rajeev Kumar ,  Nagaraj. A

IPC分类号： H05K1/02

CPC分类号： H05K1/0228 ,  H05K1/0222 ,  H05K1/0245 ,  H05K2201/09618

摘要： An apparatus for reducing interference between clock signals may include a circuit board and a first set of clock vias coupled to the circuit board. The apparatus may also include a second set of clock vias coupled to the circuit board in a linear pattern adjacent to the first set of clock vias. The first set of clock vias may transmit a first clock signal and the second set of clock vias may transmit a second clock signal with a frequency that is different from the first clock signal. The system may further include a ground via coupled to the circuit board in line with the second set of clock vias. Each ground via coupled to the circuit board may be positioned outside any region of the circuit board located between the first and second sets of clock vias. Various other apparatuses, systems, and methods are also disclosed.

摘要翻译： 用于减少时钟信号之间的干扰的装置可以包括电路板和耦合到电路板的第一组时钟通孔。 该装置还可以包括以与第一组时钟通孔相邻的线性图案耦合到电路板的第二组时钟通孔。 第一组时钟通孔可以发送第一时钟信号，并且第二组时钟通孔可以以与第一时钟信号不同的频率发送第二时钟信号。 系统还可以包括与第二组时钟通孔相配合地连接到电路板的接地通道。 耦合到电路板的每个接地通道可以位于位于第一和第二组时钟通孔之间的电路板的任何区域之外。 还公开了各种其它装置，系统和方法。

公开(公告)号：US09330992B2

公开(公告)日：2016-05-03

申请号：US14196736

申请日：2014-03-04

申请人： Renesas Electronics Corporation

发明人： Kazuyuki Nakagawa

IPC分类号： H01L23/48 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/11 ,  H01L23/367 ,  H05K1/02 ,  H01L23/00

CPC分类号： H01L23/12 ,  H01L23/367 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0253 ,  H05K1/116 ,  H05K2201/09309 ,  H05K2201/09718 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/05432 ,  H01L2924/00014 ,  H01L2924/014

摘要： A semiconductor device is provided with improved resistance to noise. Conductive planes are respectively formed over wiring layers. One wiring layer is provided with a through hole land integrally formed with a through hole wiring. In other wiring layers located over the wiring layer with the through hole land, openings are respectively formed in the conductive planes. The area of each of the openings is larger than the plane area of the through hole land.

摘要翻译： 半导体器件具有改善的抗噪声能力。 导电平面分别形成在布线层上。 一个布线层设置有与通孔布线一体形成的通孔区域。 在位于具有通孔焊盘的布线层上方的其它布线层中，在导电平面中分别形成开口。 每个开口的面积大于通孔平台的平面面积。

公开(公告)号：US20160120034A1

公开(公告)日：2016-04-28

申请号：US14992011

申请日：2016-01-10

申请人： MEDIATEK INC.

发明人： Nan-Jang Chen ,  Yau-Wai Wong

IPC分类号： H05K1/18 ,  H01L23/495 ,  H01L23/31 ,  H02H9/04

CPC分类号： H05K1/18 ,  H01L23/3185 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49558 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H02H9/046 ,  H05K1/0216 ,  H05K1/0245 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.

摘要翻译： 印刷电路板（PCB）组件包括具有芯基板的PCB，PCB的第一表面上的多个导电迹线以及PCB的第二表面上的接地层。 导电迹线包括一对差分信号迹线。 在差分信号迹线之间设置介于其间的参考迹线。 连接器设置在多个导电迹线的一端。 半导体封装安装在多个导电迹线的另一端的第一表面上。

公开(公告)号：US20160120018A1

公开(公告)日：2016-04-28

申请号：US14554923

申请日：2014-11-26

申请人： Elite Material Co., Ltd.

发明人： Ming-Chuan CHANG ,  Li-Chih YU ,  Yu-Te LIN

IPC分类号： H05K1/02 ,  H05K1/03 ,  H01P3/08

CPC分类号： H05K1/024 ,  H01P3/082 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/0353 ,  H05K1/0366 ,  H05K2201/029

摘要： A multi-layer printed circuit board comprises: at least two insulation layers, respectively having glass fiber cloth and cured resin covering thereon, the insulation layers being stacked on each other; an internal trace layer formed between two neighboring insulation layers; and an external trace layer formed on an outer surface of the outermost insulation layer; wherein the insulation layers have a dielectric constant of 3.4 or less, and the internal and external trace layers have a trace width between 40 and 75 micrometers, such that the multi-layer printed circuit board has a characteristic impedance between 45 and 55 Ω in single-ended signaling and between 90 and 110 Ω in differential signaling.

摘要翻译： 多层印刷电路板包括：分别具有玻璃纤维布和覆盖在其上的固化树脂的至少两个绝缘层，所述绝缘层彼此堆叠; 在两个相邻绝缘层之间形成的内部迹线层; 以及形成在最外绝缘层的外表面上的外部迹线层; 其中所述绝缘层具有3.4或更小的介电常数，并且所述内部和外部迹线层具有介于40和75微米之间的迹线宽度，使得所述多层印刷电路板具有在45和55之间的特征阻抗; 在单端信令和90和110之间和OHgr; 差分信号。

公开(公告)号：US20160087323A1

公开(公告)日：2016-03-24

申请号：US14558848

申请日：2014-12-03

申请人： NATIONAL TAIWAN UNIVERSITY

发明人： TZONG-LIN WU ,  CHIH-YING HSIAO ,  CHIEN-HUA HUNG

IPC分类号： H01P1/203 ,  H05K1/02 ,  H01P3/08

CPC分类号： H05K1/0218 ,  H01P1/2039 ,  H01P3/081 ,  H05K1/0227 ,  H05K1/0245 ,  H05K1/0253 ,  H05K2201/09263

摘要： The present invention is related to an electromagnetic noise filter device and an equivalent filter circuit thereof. The filter device comprises a substrate, a transmission line and a ground plane having slotted ground structure. The transmission line is configured on the top surface of the substrate, and the grounding plane is configured on the bottom surface of the substrate. At least one pair of impedance elements are configured within the slotted ground structure. The transmission line can be electromagnetic coupled to the slotted ground structure and the impedance elements so as to form an equivalent filter circuit. Thereby, the electromagnetic noises on at least one specific frequency may be absorbed by the impedance elements of the filter device so as to avoid the electromagnetic reflection induced by the electromagnetic noise and interfering the signal transmitted on the transmission line.

摘要翻译： 本发明涉及一种电磁噪声滤波器装置及其等效滤波电路。 滤波器装置包括基板，传输线和具有开槽接地结构的接地平面。 传输线配置在基板的顶表面上，接地平面配置在基板的底表面上。 至少一对阻抗元件配置在开槽的接地结构内。 传输线可以电磁耦合到开槽的接地结构和阻抗元件，以形成等效的滤波电路。 因此，至少一个特定频率的电磁噪声可能被滤波装置的阻抗元件吸收，以避免由电磁噪声引起的电磁反射并干扰传输线上传输的信号。

公开(公告)号：US20160021735A1

公开(公告)日：2016-01-21

申请号：US14534170

申请日：2014-11-06

申请人： VIA Technologies, Inc.

发明人： Sheng-Yuan Lee

IPC分类号： H05K1/02 ,  H01P3/08 ,  H05K1/11

CPC分类号： H05K1/0216 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/115 ,  H05K1/182 ,  H05K2201/042 ,  H05K2201/10189

摘要： A through-hole layout structure is suitable for a circuit board. The through-hole layout structure includes a pair of first differential through-holes, a pair of second differential through-holes, a first ground through-hole, a second ground through-hole, and a third ground through-hole, which are all arranged on a first line.The first ground through-hole is located between the pair of first differential through-holes and the pair of second differential through-holes. The pair of first differential through-holes is located between the first ground through-hole and the second ground through-hole. The pair of second differential through-holes is located between the first ground through-hole and the third ground through-hole.

摘要翻译： 通孔布局结构适用于电路板。 通孔布局结构包括一对第一差分通孔，一对第二差分通孔，第一接地通孔，第二接地通孔和第三接地通孔，这些都是 安排在第一行。 第一接地通孔位于一对第一差分通孔和一对第二差动通孔之间。 一对第一差分通孔位于第一接地通孔和第二接地通孔之间。 一对第二差分通孔位于第一接地通孔和第三接地通孔之间。

公开(公告)号：US20160007448A1

公开(公告)日：2016-01-07

申请号：US14323046

申请日：2014-07-03

申请人： AMETEK AEGIS

发明人： Kenneth G. McGillivray ,  Ricky Lee Sturdivant

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H05K1/03

CPC分类号： H05K1/0284 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H05K1/0245 ,  H05K1/0306 ,  H05K2201/09018 ,  H01L2224/45099

摘要： An electrical interconnect has a non-planar ceramic substrate with opposing first and second ends. A first conductive layer having first and second opposing sides is disposed within the ceramic substrate with one of the first and second opposing sides exposed at the first end and one of the first and second opposing sides exposed at the second end. The electrical interconnect is useful to join an integrated circuit in a hybrid package to a circuit board in high frequency communication applications.

摘要翻译： 电互连具有具有相对的第一和第二端的非平面陶瓷衬底。 具有第一和第二相对侧面的第一导电层设置在陶瓷衬底内，其中第一和第二相对侧之一在第一端处露出，第一和第二相对侧中的一个暴露在第二端。 电连接对于将混合封装中的集成电路连接到高频通信应用中的电路板是有用的。