公开(公告)号：US10289413B2

公开(公告)日：2019-05-14

申请号：US15843965

申请日：2017-12-15

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Elliot H. Mednick ,  David John Cownie

IPC: G06F9/30 ,  G06F7/483

Abstract: A hybrid floating-point arithmetic processor includes a scheduler, a hybrid register file, and a hybrid arithmetic operation circuit. The scheduler has an input for receiving floating-point instructions, and an output for providing decoded register numbers in response to the floating-point instructions. The hybrid register file is coupled to the scheduler and contains circuitry for storing a plurality of floating-point numbers each represented by a digital sign bit, a digital exponent, and an analog mantissa. The hybrid register file has an output for providing selected ones of the plurality of floating-point numbers in response to the decoded register numbers. The hybrid arithmetic operation circuit is coupled to the scheduler and to the hybrid register file, for performing a hybrid arithmetic operation between two floating-point numbers selected by the scheduler and providing a hybrid result represented by a result digital sign bit, a result digital exponent, and a result analog mantissa.

公开(公告)号：US10248497B2

公开(公告)日：2019-04-02

申请号：US14521183

申请日：2014-10-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Prashant Jayaprakash Nair ,  David A. Roberts

IPC: G06F11/10 ,  H03M13/11

Abstract: A processing system includes a memory coupled to a processor. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system.

公开(公告)号：US10067872B2

公开(公告)日：2018-09-04

申请号：US14746610

申请日：2015-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34 ,  G06F12/0862 ,  G06F12/0831 ,  G06F12/06 ,  G06F12/0811

Abstract: A plurality of memory modules, which may be used to form a heterogeneous memory system, are connected to a plurality of prefetchers. Each prefetcher is independently configured to prefetch information from a corresponding one of the plurality of memory modules in response to feedback from the corresponding one of the plurality of memory modules.

公开(公告)号：US20180143905A1

公开(公告)日：2018-05-24

申请号：US15358318

申请日：2016-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Ehsan Fatehi

IPC: G06F12/0815 ,  G06F12/084 ,  G06F12/0817 ,  G06F13/16

CPC classification number: G06F12/0815 ,  G06F12/0822 ,  G06F12/0824 ,  G06F12/0826 ,  G06F12/084 ,  G06F13/1615 ,  G06F2212/1024 ,  G06F2212/314 ,  G06F2212/502 ,  G06F2212/621

Abstract: A non-uniform memory access system includes several nodes that each have one or more processors, caches, local main memory, and a local bus that connects a node's processor(s) to its memory. The nodes are coupled to one another over a collection of point-to-point interconnects, thereby permitting processors in one node to access data stored in another node. Memory access time for remote memory takes longer than local memory because remote memory accesses have to travel across a communications network to arrive at the requesting processor. In some embodiments, inter-cache and main-memory-to-cache latencies are measured to determine whether it would be more efficient to satisfy memory access requests using cached copies stored in caches of owning nodes or from main memory of home nodes.

公开(公告)号：US09934148B2

公开(公告)日：2018-04-03

申请号：US14747967

申请日：2015-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Sergey Blagodurov

IPC: G06F12/10 ,  G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6024

Abstract: A memory module stores memory access metadata reflecting information about memory accesses to the memory module. The memory access metadata can indicate the number of times a particular unit of data (e.g., a row of data, a unit of data corresponding to a cache line, and the like) has been read, written, had one or more of its bits flipped, and the like. Modifications to the embedded access metadata can be made by a control module at the memory module itself, thereby reducing overhead at a processor core. In addition, the control module can be configured to record different access metadata for different memory locations of the memory module.

公开(公告)号：US20170308297A1

公开(公告)日：2017-10-26

申请号：US15136851

申请日：2016-04-22

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Michael Ignatowski

IPC: G06F3/06 ,  G06F12/1045

CPC classification number: G06F3/061 ,  G06F3/0653 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/1027 ,  G06F12/1045 ,  G06F2212/1041 ,  G06F2212/68 ,  G06F2212/684

Abstract: Described are a method and processing apparatus to tag and track objects related to memory allocation calls. An application or software adds a tag to a memory allocation call to enable object level tracking. An entry is made into an object tracking table, which stores the tag and a variety of statistics related to the object and associated memory devices. The object statistics may be queried by the application to tune power/performance characteristics either by the application making runtime placement decisions, or by off-line code tuning based on a previous run. The application may add a tag to a memory allocation call to specify the type of memory characteristics requested based on the object statistics.

公开(公告)号：US20170212760A1

公开(公告)日：2017-07-27

申请号：US15353161

申请日：2016-11-16

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Meenakshi Sundaram Bhaskaran ,  Elliot H. Mednick ,  David A. Roberts ,  Anthony Asaro ,  Amin Farmahini-Farahani

IPC: G06F9/30 ,  G06F12/0817 ,  G06F12/0875 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3005 ,  G06F9/3016 ,  G06F9/3802 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/6028

Abstract: A system and method for reducing latencies of main memory data accesses are described. A non-blocking load (NBLD) instruction identifies an address of requested data and a subroutine. The subroutine includes instructions dependent on the requested data. A processing unit verifies that address translations are available for both the address and the subroutine. The processing unit continues processing instructions with no stalls caused by younger-in-program-order instructions waiting for the requested data. The non-blocking load unit performs a cache coherent data read request on behalf of the NBLD instruction and requests that the processing unit perform an asynchronous jump to the subroutine upon return of the requested data from lower-level memory.

公开(公告)号：US20170083474A1

公开(公告)日：2017-03-23

申请号：US14862011

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh R. Meswani ,  David A. Roberts ,  Yasuko Eckert ,  Kapil Dev ,  John Kalamatianos ,  Indrani Paul

IPC: G06F13/42 ,  G06F13/18 ,  G06F12/08

CPC classification number: G06F13/4234 ,  G06F12/084 ,  G06F12/0862 ,  G06F13/18 ,  G06F2212/314 ,  G06F2212/603 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A plurality of first controllers operate according to a plurality of access protocols to control a plurality of memory modules. A second controller receives access requests that target the plurality of memory modules and selectively provides the access requests and control information to the plurality of first controllers based on physical addresses in the access requests. The second controller generates the control information for the first controllers based on statistical representations of the access requests to the plurality of memory modules.

公开(公告)号：US20170083444A1

公开(公告)日：2017-03-23

申请号：US14862030

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kapil Dev ,  Mitesh R. Meswani ,  David A. Roberts ,  Yasuko Eckert ,  Indrani Paul ,  John Kalamatianos

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F12/0871 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/121 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/2515 ,  G06F2212/502 ,  G06F2212/601

Abstract: A cache controller to configure a portion of a first memory as cache for a second memory responsive to an indicator of locality of memory access requests to the second memory. The indicator of locality determines a probability that a location of a memory access request to the second memory is predictable based upon at least one previous memory access request. The cache controller may determine a size of the cache based on a value of the indicator of locality or modify the size of the cache in response to changes in the value of the indicator of locality.

公开(公告)号：US20160380635A1

公开(公告)日：2016-12-29

申请号：US14751947

申请日：2015-06-26

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: H03K19/177 ,  H03K19/00

CPC classification number: H03K19/17728 ,  G06F15/7892 ,  H03K19/0008 ,  H03K19/1776 ,  H03K19/17776

Abstract: A programmable device comprises one or more programming regions, each comprising a plurality of configurable logic blocks, where each of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block via a programmable interconnect fabric. The programmable device further comprises configuration logic configured to, in response to an instruction in an instruction stream, reconfigure hardware in one or more of the configurable logic blocks in a programming region independently from any of the other programming regions.

Abstract translation: 可编程设备包括一个或多个编程区域，每个编程区域包括多个可配置逻辑块，其中多个可配置逻辑块中的每一个可经由可编程互连结构选择性地连接到任何其它可配置逻辑块。 可编程设备还包括配置逻辑，配置为响应于指令流中的指令，在编程区域中的一个或多个可配置逻辑块中独立于任何其他编程区域重新配置硬件。