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139 条记录 (耗时 0.041 秒)

    Semiconductor package and method for fabricating the same
    72.
    发明申请
    Semiconductor package and method for fabricating the same 审中-公开
    半导体封装及其制造方法

    公开(公告)号：US20090102063A1

    公开(公告)日：2009-04-23

    申请号：US12287936

    申请日：2008-10-14

    申请人： Chun-Yuan Lee ,  Chien Ping Huang ,  Yu-Ting Lai ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

    发明人： Chun-Yuan Lee ,  Chien Ping Huang ,  Yu-Ting Lai ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

    IPC分类号： H01L23/48 ,  H01L21/00

    CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： This invention provides a semiconductor package and a method for fabricating the same. The method includes: forming a first resist layer on a metal carrier; forming a plurality of openings penetrating the first resist layer; forming a conductive metal layer in the openings; removing the first resist layer; covering the metal carrier having the conductive metal layer with a dielectric layer; forming blind vias in the dielectric layer to expose a portion of the conductive metal layer; forming conductive circuit on the dielectric layer and conductive posts in the blind vias, such that the conductive circuit is electrically connected to the conductive metal layer via the conductive posts; electrically connecting at least one chip to the conductive circuit; forming an encapsulant for encapsulating the chip and the conductive circuit; and removing the metal carrier, thereby allowing a semiconductor package to be formed without a chip carrier. Given the conductive posts, both the conductive circuit and conductive metal layer are efficiently coupled to the dielectric layer to prevent delamination. Further, downsizing the blind vias facilitates the fabrication process and cuts the fabrication cost.

    摘要翻译： 本发明提供一种半导体封装及其制造方法。 该方法包括：在金属载体上形成第一抗蚀剂层; 形成穿过所述第一抗蚀剂层的多个开口; 在所述开口中形成导电金属层; 去除第一抗蚀剂层; 用介电层覆盖具有导电金属层的金属载体; 在介电层中形成盲孔以暴露导电金属层的一部分; 在介电层上形成导电电路和在盲孔中的导电柱，使得导电电路经由导电柱电连接到导电金属层; 将至少一个芯片电连接到所述导电电路; 形成用于封装所述芯片和所述导电电路的密封剂; 并且去除金属载体，从而允许在没有芯片载体的情况下形成半导体封装。 给定导电柱，导电电路和导电金属层都有效地耦合到电介质层以防止分层。 此外，缩小盲孔通孔有助于制造工艺并降低制造成本。

    Heat dissipating semiconductor package and fabrication method therefor
    73.
    发明申请
    Heat dissipating semiconductor package and fabrication method therefor 审中-公开
    散热半导体封装及其制造方法

    公开(公告)号：US20080122071A1

    公开(公告)日：2008-05-29

    申请号：US11986362

    申请日：2007-11-21

    申请人： Wen-Tsung Tseng ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Chih-Wei Chang ,  Cheng-Hsu Hsiao

    发明人： Wen-Tsung Tseng ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Chih-Wei Chang ,  Cheng-Hsu Hsiao

    IPC分类号： H01L23/373

    CPC分类号： H01L23/3128 ,  H01L21/568 ,  H01L23/4334 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/15311

    摘要： A heat dissipating semiconductor package and the fabrication method therefor are provided. The fabrication method for the heat dissipating semiconductor package mainly includes steps of: containing a substrate having a chip mounted thereon in an aperture of a carrier, wherein the carrier has an electroconductive layer; allowing a heat dissipating structure having supporting portions to be mounted on and electrically connected to the electroconductive layer of the carrier via the supporting portions thereof while heat dissipating structure being mounted on the chip; after an encapsulation process and removing a part of the encapsulant above the heat dissipating sheet by lapping to expose a surface of the heat dissipating structure from the encapsulant, depositing and forming a metal passivation layer on the surface of the heat dissipating structure by electroplating for preventing the heat dissipating structure from oxidizing.

    摘要翻译： 提供一种散热半导体封装及其制造方法。 用于散热半导体封装的制造方法主要包括以下步骤：在载体的孔中容纳其上安装有芯片的基板，其中载体具有导电层; 允许散热结构，其具有支撑部分，其安装在载体的导电层上并通过其支撑部分电连接，同时散热结构安装在芯片上; 在封装工艺之后并且通过研磨去除散热片上方的一部分密封剂，以从密封剂暴露出散热结构的表面，在散热结构的表面上沉积和形成金属钝化层，通过电镀防止 散热结构从氧化。

    Method for fabricating semiconductor packages
    75.
    发明授权
    Method for fabricating semiconductor packages 有权
    半导体封装的制造方法

    公开(公告)号：US07348211B2

    公开(公告)日：2008-03-25

    申请号：US11117158

    申请日：2005-04-27

    申请人： Ying-Ren Lin ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

    发明人： Ying-Ren Lin ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

    IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44

    CPC分类号： H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.

    摘要翻译： 提出了制造半导体封装的方法。 制备各自具有芯片的多个基板。 每个衬底具有与半导体封装的预定长度和宽度相似的长度和宽度。 制备具有多个开口的载体。 每个开口的长度和宽度大于衬底。 基板定位在相应的开口中，基板和载体之间的间隙被密封。 执行成型工艺以在每个开口上形成密封剂以封装芯片。 由密封剂覆盖的载体上的区域的长度和宽度大于开口的宽度。 在执行脱模工艺之后，通过单片化工艺形成多个半导体封装，以根据半导体封装的预定尺寸沿着每个衬底的大致边缘切割。 避免了衬底材料的浪费。

    Semiconductor package substrate
    77.
    发明申请
    Semiconductor package substrate 有权
    半导体封装基板

    公开(公告)号：US20070273026A1

    公开(公告)日：2007-11-29

    申请号：US11701767

    申请日：2007-02-02

    申请人： Hsieh-Tsung Tien ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

    发明人： Hsieh-Tsung Tien ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

    IPC分类号： H01L23/488

    CPC分类号： H01L23/49827 ,  H01L23/64 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718 ,  H01L2924/00

    摘要： A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

    摘要翻译： 提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。 因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

    Method for fabricating semiconductor packages
    80.
    发明申请
    Method for fabricating semiconductor packages 有权
    半导体封装的制造方法

    公开(公告)号：US20050287707A1

    公开(公告)日：2005-12-29

    申请号：US11117158

    申请日：2005-04-27

    申请人： Ying-Ren Lin ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

    发明人： Ying-Ren Lin ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

    IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31

    CPC分类号： H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.

    摘要翻译： 提出了制造半导体封装的方法。 制备各自具有芯片的多个基板。 每个衬底具有与半导体封装的预定长度和宽度相似的长度和宽度。 制备具有多个开口的载体。 每个开口的长度和宽度大于衬底。 基板定位在相应的开口中，基板和载体之间的间隙被密封。 执行成型工艺以在每个开口上形成密封剂以封装芯片。 由密封剂覆盖的载体上的区域的长度和宽度大于开口的宽度。 在执行脱模工艺之后，通过单片化工艺形成多个半导体封装，以根据半导体封装的预定尺寸沿着每个衬底的大致边缘切割。 避免了衬底材料的浪费。