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    Methods for forming FinFETS having a capping layer for reducing punch through leakage
    73.
    发明授权
    Methods for forming FinFETS having a capping layer for reducing punch through leakage 有权
    用于形成具有用于减少穿孔渗漏的覆盖层的FinFETS的方法

    公开(公告)号：US09595583B2

    公开(公告)日：2017-03-14

    申请号：US15060052

    申请日：2016-03-03

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hoon Kim ,  Min Gyu Sung

    IPC: H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238

    CPC classification number: H01L29/1083 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

    Abstract: A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer.

    Abstract translation: 用于形成具有用于减少穿通漏电的封盖层的FinFET的方法包括提供具有设置在半导体衬底上的半导体衬底和鳍的中间半导体结构。 覆盖层设置在翅片上方，并且隔离填充物设置在覆盖层上。 去除隔离填充物和覆盖层的一部分以露出翅片的上表面部分。 突出层和鳍的下部限定了界面偶极层势垒，所述覆盖层的一部分可操作以提供增加的负电荷或增加与所述鳍相邻的正电荷，以减少与不具有 盖层。

    Co-fabrication of non-planar semiconductor devices having different threshold voltages
    74.
    发明授权
    Co-fabrication of non-planar semiconductor devices having different threshold voltages 有权
    具有不同阈值电压的非平面半导体器件的共同制造

    公开(公告)号：US09552992B2

    公开(公告)日：2017-01-24

    申请号：US14634483

    申请日：2015-02-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hoon Kim ,  Min-Gyu Sung ,  Chanro Park ,  Ruilong Xie

    IPC: H01L21/28 ,  H01L29/40 ,  H01L21/02

    CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/517

    Abstract: Co-fabricating non-planar (i.e., three-dimensional) semiconductor devices with different threshold voltages includes providing a starting semiconductor structure, the structure including a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, at least two gate structures encompassing a portion of the raised structures, each gate structure including a gate opening lined with dielectric material and partially filled with work function material, a portion of the work function material being recessed. The co-fabrication further includes creating at least one conformal barrier layer in one or more and less than all of the gate openings, filling the gate openings with conductive material, and modifying the work function of at least one and less than all of the filled gate structures.

    Abstract translation: 共同制造具有不同阈值电压的非平面（即，三维）半导体器件包括提供起始半导体结构，该结构包括半导体衬底，耦合到衬底的多个凸起半导体结构，至少两个栅极结构， 每个栅极结构包括一个衬有介电材料并部分填充有功函材料的栅极开口，一部分功函材料被凹入。 共同制造还包括在一个或多个且少于所有的栅极开口中产生至少一个共形阻挡层，用导电材料填充栅极开口，以及修改至少一个且小于所有填充的栅极开口的功函数 门结构。

    METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL IN A TRENCH FORMED ABOVE A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES
    78.
    发明申请
    METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL IN A TRENCH FORMED ABOVE A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES 有权
    在上述形成的半导体器件和结果器件中形成EPI半导体材料的方法

    公开(公告)号：US20150318398A1

    公开(公告)日：2015-11-05

    申请号：US14267216

    申请日：2014-05-01

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Min Gyu Sung

    IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

    CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

    Abstract: One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, wherein a first portion of the gate structure is positioned above the active region and second portions of the gate structure are positioned above an isolation region formed in the substrate, forming a sidewall spacer adjacent opposite sides of the first portion of the gate structure so as to define first and second continuous epi formation trenches comprised of the spacer that extend for less than the axial length of the gate structure, and forming an epi semiconductor material on the active region within each of the first and second continuous epi formation trenches.

    Abstract translation: 所公开的一种方法包括在半导体衬底的有源区上方形成栅极结构，其中栅极结构的第一部分位于有源区上方，栅极结构的第二部分位于形成的隔离区的上方 在所述衬底中，形成邻近所述栅极结构的第一部分的相对侧面的侧壁间隔物，以便限定由所述间隔物组成的第一和第二连续外延形成沟槽，所述沟槽延伸小于所述栅极结构的轴向长度，并形成 在第一和第二连续外延形成沟槽的每一个内的有源区域上的外延半导体材料。

    METHODS OF FORMING A METAL CAP LAYER ON COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE
    79.
    发明申请
    METHODS OF FORMING A METAL CAP LAYER ON COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE 有权
    在集成电路设备上形成基于铜基导电结构的金属层的方法

    公开(公告)号：US20150255339A1

    公开(公告)日：2015-09-10

    申请号：US14201255

    申请日：2014-03-07

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Hoon Kim ,  Christian Witt ,  Larry Zhao

    IPC: H01L21/768 ,  H01L21/306

    CPC classification number: H01L21/76882 ,  H01L21/30625 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One method includes forming a barrier layer in a trench/opening in an insulating material, forming a first region of a copper material above the barrier layer, forming a metal layer in the trench/opening on the first region of copper material, forming a second region of copper material on the metal layer, performing at least one CMP process to remove any materials positioned above a planarized upper surface of the layer of insulating material outside of the trench/opening so as to thereby define a structure comprised of the metal layer positioned between the first and second regions of copper material, forming a dielectric cap layer above the layer of insulating material and above the structure, and performing a metal diffusion anneal process to form a metal cap layer adjacent at least the upper surface of a conductive copper structure.

    Abstract translation: 一种方法包括在绝缘材料的沟槽/开口中形成阻挡层，在阻挡层之上形成铜材料的第一区域，在铜材料的第一区域上的沟槽/开口中形成金属层，形成第二层 在金属层上的铜材料区域，执行至少一个CMP工艺以去除位于沟槽/开口外部的绝缘材料层的平坦化上表面上方的任何材料，从而限定由金属层定位的结构 在铜材料的第一和第二区域之间，在绝缘材料层之上并在结构之上形成电介质盖层，并进行金属扩散退火工艺以形成至少与导电铜结构的上表面相邻的金属盖层 。

    Methods of forming gate structures for transistor devices for CMOS applications
    80.
    发明授权
    Methods of forming gate structures for transistor devices for CMOS applications 有权
    为CMOS应用形成晶体管器件的栅极结构的方法

    公开(公告)号：US09105497B2

    公开(公告)日：2015-08-11

    申请号：US14017485

    申请日：2013-09-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

    IPC: H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

    Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

    Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

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