公开(公告)号：US20190051488A1

公开(公告)日：2019-02-14

申请号：US16057014

申请日：2018-08-07

Applicant: Infineon Technologies AG

Inventor： Werner Schustereder ,  Moriz Jelinek ,  Hans-Joachim Schulze

IPC: H01J37/20 ,  H01J37/317 ,  H01J37/147 ,  H01L21/265 ,  H01L21/04 ,  H01L21/266 ,  H01L21/225 ,  C23C14/48 ,  C23C14/04 ,  C23C14/54

Abstract: An implantation apparatus includes a scanning assembly that effects a relative movement between an ion beam and a semiconductor substrate along a first scan direction and along a second scan direction orthogonal to the first scan direction. A tilt assembly changes a tilt angle θ between a beam axis of the ion beam and a normal to a main surface of the semiconductor substrate from a first tilt angle θ1 to a second tilt angle θ2, wherein an angular span Δθ between the first tilt angle θ1 and the second tilt angle θ2 is at least 5°. A control unit controls the tilt assembly to continuously change the tilt angle θ during the relative movement between the ion beam and the semiconductor substrate.

公开(公告)号：US20190013210A1

公开(公告)日：2019-01-10

申请号：US16116210

申请日：2018-08-29

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Irmgard Escher-Poeppel ,  Stephanie Fassl ,  Paul Ganitzer ,  Gerhard Poeppel ,  Werner Schustereder ,  Harald Wiedenhofer

IPC: H01L21/324 ,  H01L21/285 ,  H01L21/225 ,  H01L21/04 ,  H01L21/321 ,  H01L21/268 ,  H01L23/31

CPC classification number: H01L21/324 ,  H01L21/0455 ,  H01L21/0485 ,  H01L21/2254 ,  H01L21/2258 ,  H01L21/268 ,  H01L21/28512 ,  H01L21/28575 ,  H01L23/3157

Abstract: Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material, wherein the method comprises: providing an electronic device comprising a multilayer structure and being at least partially encapsulated by an encapsulation material; and locally introducing energy into the multilayer structure for reducing a sheet resistance.

公开(公告)号：US10083835B2

公开(公告)日：2018-09-25

申请号：US15634406

申请日：2017-06-27

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Anton Mauder ,  Roland Rupp ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: H01L21/263 ,  H01L21/265 ,  H01L21/04 ,  H01L21/3065 ,  H01L21/266 ,  H01L29/739 ,  H01L21/67 ,  H01L21/28 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L29/812 ,  H01L29/808 ,  H01L29/10

CPC classification number: H01L21/2633 ,  H01L21/047 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/049 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28114 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/67069 ,  H01L29/045 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/8128

Abstract: By directing an ion beam with a beam divergence θ on a process surface of a semiconductor substrate, parallel electrode trenches are formed in the semiconductor substrate. A center axis of the directed ion beam is tilted to a normal to the process surface at a tilt angle α, wherein at least one of the tilt angle α and the beam divergence θ is not equal to zero. The semiconductor substrate is moved along a direction parallel to the process surface during formation of the electrode trenches. A conductive electrode is formed in the electrode trenches, wherein first sidewalls of the electrode trenches are tilted to the normal by a first slope angle φ1 with φ1 =(α+θ/2) and second sidewalls are tilted to the normal by a second slope angle φ2 with φ2 =(α−θ/2).

公开(公告)号：US10037887B2

公开(公告)日：2018-07-31

申请号：US15435034

申请日：2017-02-16

Applicant: Infineon Technologies AG

Inventor： Michael Brugger ,  Moriz Jelinek ,  Johannes Georg Laven ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: H01L21/66 ,  H01L21/265

CPC classification number: H01L21/26586 ,  H01L22/12 ,  H01L22/20

Abstract: A method for implanting ions into a semiconductor substrate includes performing a test implantation of ions into a semiconductor substrate. The ions of the test implantation are implanted with a first implantation angle range over the semiconductor substrate. Further, the method includes determining an implantation angle offset based on the semiconductor substrate after the test implantation and adjusting a tilt angle of the semiconductor substrate with respect to an implantation direction based on the determined implantation angle offset. Additionally, the method includes performing at least one target implantation of ions into the semiconductor substrate after the adjustment of the tilt angle. The ions of the at least one target implantation are implanted with a second implantation angle range over the semiconductor substrate. Further, the first implantation angle range is larger than the second implantation angle range.

公开(公告)号：US20180005830A1

公开(公告)日：2018-01-04

申请号：US15634406

申请日：2017-06-27

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Anton Mauder ,  Roland Rupp ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: H01L21/263 ,  H01L29/78 ,  H01L29/739 ,  H01L29/423 ,  H01L21/67 ,  H01L21/04 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/266 ,  H01L21/265 ,  H01L29/812 ,  H01L29/40

CPC classification number: H01L21/2633 ,  H01L21/047 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28114 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/67069 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/8128

Abstract: By directing an ion beam with a beam divergence θ on a process surface of a semiconductor substrate, parallel electrode trenches are formed in the semiconductor substrate. A center axis of the directed ion beam is tilted to a normal to the process surface at a tilt angle α, wherein at least one of the tilt angle α and the beam divergence θ is not equal to zero. The semiconductor substrate is moved along a direction parallel to the process surface during formation of the electrode trenches. A conductive electrode is formed in the electrode trenches, wherein first sidewalls of the electrode trenches are tilted to the normal by a first slope angle φ 1 with φ 1=(α+0/2) and second sidewalls are tilted to the normal by a second slope angle φ 2 with φ 2=(α−θ/2).

公开(公告)号：US09812563B2

公开(公告)日：2017-11-07

申请号：US15182244

申请日：2016-06-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Markus Zundel ,  Karl-Heinz Bach ,  Franz Hirler ,  Christian Kampen ,  Werner Schustereder

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L29/7813 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/324 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66734

Abstract: A transistor cell includes, in a semiconductor body, a drift region of a first doping type, a source region of the first doping type, a body region of a second doping type, and a drain region of the first doping type. The body region is arranged between the source and drift regions. The drift region is arranged between the body and drain regions. A gate electrode is adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode is dielectrically insulated from the drift region by a field electrode dielectric. The drift region includes an avalanche region having a higher doping concentration than sections of the drift region adjacent the avalanche region and which is spaced apart from the field electrode dielectric in a direction perpendicular to the current flow direction. The field electrode is arranged in a needle-shaped trench.

公开(公告)号：US20170170028A1

公开(公告)日：2017-06-15

申请号：US15379243

申请日：2016-12-14

Applicant: Infineon Technologies AG

Inventor： Werner Schustereder ,  Helmut Oefner ,  Hans-Joachim Schulze ,  Sandeep Walia

IPC: H01L21/322 ,  H01L21/02 ,  H01L21/306 ,  H01L21/223

CPC classification number: H01L21/3225 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/30604

Abstract: Disclosed is a method for processing a semiconductor wafer. The method includes forming an oxygen containing region in the semiconductor wafer, wherein forming the oxygen containing region includes introducing oxygen via a first surface into the semiconductor wafer. The method further includes creating vacancies at least in the oxygen containing region and annealing at least the oxygen containing region in an annealing process so as to form oxygen precipitates.

公开(公告)号：US09634086B2

公开(公告)日：2017-04-25

申请号：US14952337

申请日：2015-11-25

Applicant: Infineon Technologies AG

Inventor： Moriz Jelinek ,  Johannes Georg Laven ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: H01L21/265 ,  C30B31/22 ,  H01L29/06 ,  H01L21/66 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324

CPC classification number: H01L29/0634 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3242 ,  H01L22/14 ,  H01L22/20 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/407 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

Abstract: A first doped region is formed in a single crystalline semiconductor substrate. Light ions are implanted through a process surface into the semiconductor substrate to generate crystal lattice vacancies between the first doped region and the process surface, wherein a main beam axis of an implant beam used for implanting the light ions deviates by at most 1.5 degree from a main crystal direction along which channeling of the light ions occurs. A second doped region with a conductivity type opposite to the first doped region is formed based on the crystal lattice vacancies and hydrogen atoms.

公开(公告)号：US20160372329A1

公开(公告)日：2016-12-22

申请号：US15178039

申请日：2016-06-09

Applicant: Infineon Technologies AG

Inventor： Moriz Jelinek ,  Naveen Goud Ganagona ,  Johannes Georg Laven ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: H01L21/265 ,  H01L29/10 ,  H01L21/66 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L29/1095 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/3242 ,  H01L21/67248 ,  H01L22/26 ,  H01L29/0878 ,  H01L29/167 ,  H01L29/32 ,  H01L29/6609 ,  H01L29/66333 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/861

Abstract: A method for forming a semiconductor device includes implanting a predefined dose of protons into a semiconductor substrate. Further, the method comprises controlling a temperature of the semiconductor substrate during the implantation of the predefined dose of protons so that the temperature of the semiconductor substrate is within a target temperature range for more than 70% of an implant process time used for implanting the predefined dose of protons. The target temperature range reaches from a lower target temperature limit to an upper target temperature limit. Further, the lower target temperature limit is equal to a target temperature minus 30° C. and the upper target temperature limit is equal to the target temperature plus 30° C. and the target temperature is higher than 80° C.

Abstract translation: 一种用于形成半导体器件的方法包括将预定剂量的质子注入到半导体衬底中。 此外，该方法包括在注入预定剂量的质子期间控制半导体衬底的温度，使得半导体衬底的温度在用于植入预定义的植入处理时间的植入物处理时间的70％以上在目标温度范围内 质子剂量。 目标温度范围从较低的目标温度限制到达目标温度上限。 此外，较低的目标温度限制等于目标温度减去30℃，上限温度等于目标温度加30℃，目标温度高于80℃。

公开(公告)号：US09349799B2

公开(公告)日：2016-05-24

申请号：US14825231

申请日：2015-08-13

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Josef Georg Bauer ,  Mario Barusic ,  Oliver Humbel ,  Hans Millonig ,  Werner Schustereder

IPC: H01L21/332 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739 ,  H01L29/08 ,  H01L21/266 ,  H01L21/225 ,  H01L21/263

CPC classification number: H01L29/1095 ,  H01L21/225 ,  H01L21/2636 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/3221 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/167 ,  H01L29/207 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/732 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/8611

Abstract: Disclosed are a method and a semiconductor device. The method includes implanting recombination center atoms via a first surface into a semiconductor body, and causing the implanted recombination center atoms to diffuse in the semiconductor body in a first diffusion process.

Abstract translation: 公开了一种方法和半导体器件。 该方法包括通过第一表面将复合中心原子注入到半导体本体中，并且使得注入的复合中心原子在第一扩散过程中在半导体本体中扩散。