公开(公告)号：US20170104060A1

公开(公告)日：2017-04-13

申请号：US14880362

申请日：2015-10-12

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/02603 ,  H01L21/02164 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/775

Abstract: A method forms first and second sets of fins. The first set includes a first stack of layer pairs where each layer pair contains a layer of Si having a first thickness and a layer of SiGe having a second thickness. The second set of fins includes a second stack of layer pairs where at least one layer pair contains a layer of Si having the first thickness and a layer of SiGe having a third thickness greater than the second thickness. The method further includes removing the layers of SiGe from the first stack leaving first stacked Si nanowires spaced apart by a first distance and from the second stack leaving second stacked Si nanowires spaced apart by a second distance corresponding to the third thickness. The method further includes forming a first dielectric layer on the first nanowires and a second, thicker dielectric layer on the second nanowires.

公开(公告)号：US20170069715A1

公开(公告)日：2017-03-09

申请号：US15354142

申请日：2016-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Isaac Lauer ,  Tenko Yamashita ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/562 ,  B82Y10/00 ,  H01L21/02403 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

Abstract translation: 纳米线装置包括形成在基板上的第一部件和与基板上的第一部件分开设置的第二部件。 纳米线被配置为将第一部件连接到第二部件。 沿着纳米线的跨度形成锚垫，并且构造成沿着跨度支撑纳米线以防止下垂。

公开(公告)号：US09570443B1

公开(公告)日：2017-02-14

申请号：US14948737

申请日：2015-11-23

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/8256 ,  H01L21/02

CPC classification number: H01L21/8258 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02617 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8252 ,  H01L21/8256 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/7847 ,  H01L29/7849 ,  H01L29/785

Abstract: In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.

Abstract translation: 在一个示例中，器件包括p型场效应晶体管区域和n型场效应晶体管区域。 p型场效应晶体管区域包括至少一个包括应变锗的鳍。 n型场效应晶体管区域还包括至少一个包括应变锗的鳍。

公开(公告)号：US20170040223A1

公开(公告)日：2017-02-09

申请号：US15225157

申请日：2016-08-01

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L29/16 ,  H01L29/161 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161

Abstract: A method includes providing a substrate that underlies a layer of SiGe; forming a plurality of fins in the layer of SiGe. Each formed fin has a fin shape and fin location preserving hard mask layer on a top surface. The method also includes depositing Si on a first subset of the set of fins in what will be an nFET area; performing a Si—Ge inter-mixing process on the first subset of fins to reduce a concentration of Ge in the first subset while producing a Si—Ge intermix layer; removing the Si—Ge intermix layer leaving the first subset of fins having the reduced concentration of Ge, and forming a second subset of fins in what will be a pFET area. The second subset is also formed from the layer of SiGe and has a greater percentage of Ge than a percentage of Ge in the first subset of fins.

Abstract translation: 一种方法包括提供在SiGe层下面的衬底; 在SiGe层中形成多个翅片。 每个形成的翅片具有在顶部表面上保持硬掩模层的翅片形状和翅片位置。 该方法还包括在nFET区域中在该组鳍片的第一子集上沉积Si; 在鳍的第一子集上执行Si-Ge相互混合处理以减少第一子集中的Ge的浓度，同时产生Si-Ge混合层; 去除离开具有降低的Ge浓度的散热片的第一子集的Si-Ge混合层，以及在将是pFET区域的情况下形成翅片的第二子集。 第二子集还由SiGe层形成，并且在第一子鳍片中Ge的百分比大于Ge的百分比。

公开(公告)号：US20170025498A1

公开(公告)日：2017-01-26

申请号：US15283670

申请日：2016-10-03

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08 ,  H01L29/20 ,  H01L21/306 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L21/30612 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1087 ,  H01L29/20 ,  H01L29/423 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78681 ,  H01L29/78696

Abstract: Embodiments of the invention include a method for fabricating a nano-ribbon transistor device and the resulting structure. A nano-ribbon transistor device including a substrate, a nano-ribbon channel, a core region in the center of the nano-ribbon channel, a gate formed around the nano-ribbon channel, a spacer formed on each sidewall of the gate, and a source and drain region epitaxially formed adjacent to each spacer is provided. The core region in the center of the nano-ribbon channel is selectively etched. A dielectric material is deposited on the exposed portions of the nano-ribbon channel. A back-bias control region is formed on the dielectric material within the core of the nano-ribbon channel and on the substrate adjacent to the nano-ribbon transistor device. A metal contact is formed in the back-bias control region.

Abstract translation: 本发明的实施例包括一种用于制造纳米带状晶体管器件的方法及其结果。 一种纳米带状晶体管器件，包括衬底，纳米带通道，纳米带通道中心的芯区域，形成在纳米带通道周围的栅极，形成在栅极的每个侧壁上的隔离物，以及 提供了与每个间隔物相邻外延形成的源极和漏极区域。 选择性地蚀刻纳米带通道中心的核心区域。 介电材料沉积在纳米带通道的暴露部分上。 在纳米带通道的芯内的电介质材料上和与纳米带晶体管器件相邻的衬底上形成背偏压控制区。 在背偏压控制区域中形成金属接触。

公开(公告)号：US20160380094A1

公开(公告)日：2016-12-29

申请号：US14749827

申请日：2015-06-25

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795

Abstract: A method is provided for forming an integrated circuit. A doped silicon layer is formed on a silicon substrate. A silicon-germanium layer is subsequently formed on the doped silicon layer. The silicon-germanium layer is pattered to form a silicon-germanium feature. A silicon shell is formed on the silicon-germanium feature. At least a portion of the dopes silicon layer is converted to a porous silicon layer. Following the last step, the silicon shell is tensily stressed, making it a good candidate for use as a channel feature in an n-type field effect transistor.

Abstract translation: 提供了一种用于形成集成电路的方法。 在硅衬底上形成掺杂硅层。 随后在掺杂硅层上形成硅 - 锗层。 硅锗层被图案化以形成硅 - 锗特征。 在硅 - 锗特征上形成硅壳。 将掺杂硅层的至少一部分转化为多孔硅层。 在最后一步之后，硅壳是紧张的，使其成为用作n型场效应晶体管中的通道特征的良好候选者。

公开(公告)号：US20160380003A1

公开(公告)日：2016-12-29

申请号：US15136133

申请日：2016-04-22

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/51 ,  H01L21/02 ,  H01L29/49 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02554 ,  H01L21/302 ,  H01L21/32 ,  H01L21/845 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device, comprises patterning a first layer on a substrate to form at least one fin, patterning a second layer under the first layer to remove a portion of the second layer on sides of the at least one fin, forming a sacrificial gate electrode on the at least one fin, and a spacer on the sacrificial gate electrode, selectively removing the sacrificial gate electrode, depositing an oxide layer on top and side portions of the at least one fin corresponding to a channel region of the at least one fin, performing thermal oxidation to condense the at least one fin in the channel region until a bottom portion of the at least one fin is undercut, and stripping a resultant oxide layer from the thermal oxidation, leaving a gap in the channel region between a bottom portion of the at least one fin and the second layer.

Abstract translation: 一种用于制造鳍状场效应晶体管（FinFET）器件的方法，包括对衬底上的第一层进行图案化以形成至少一个翅片，在第一层下方图案化第二层以去除第二层的第二层的一部分 至少一个翅片，在所述至少一个翅片上形成牺牲栅极电极，以及在所述牺牲栅极电极上的间隔物，选择性地去除所述牺牲栅电极，在所述至少一个翅片的顶部和侧部上沉积氧化物层， 所述至少一个翅片的通道区域，进行热氧化以使所述通道区域中的所述至少一个翅片冷凝，直到所述至少一个翅片的底部部分被切下，并且从所述热氧化中剥离所得到的氧化物层， 在至少一个翅片的底部和第二层之间的通道区域中的间隙。

公开(公告)号：US09530772B1

公开(公告)日：2016-12-27

申请号：US14820126

申请日：2015-08-06

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823437 ,  H01L28/20 ,  H01L29/161 ,  H01L29/42376 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor device comprises forming a first dummy gate layer on a substrate, forming a second dummy gate layer on the substrate adjacent the first dummy gate layer, wherein the second dummy gate layer comprises a material which is capable of being selectively etched with respect a material of the first dummy gate layer, and patterning each of the first and second dummy gate layers into a plurality of first dummy gate stacks and a plurality of second dummy gate stacks, respectively, wherein the first dummy gate stacks are each wider along a gate length direction than each of the second dummy gate stacks, wherein the patterning is performed using a reactive ion etch (RIE) process that results in different lateral trimming between the first and second dummy gate layers.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成第一伪栅极层，在与第一虚拟栅极层相邻的衬底上形成第二虚拟栅极层，其中第二虚拟栅极层包括能够被选择性蚀刻的材料 相对于第一虚拟栅极层的材料，并且分别将第一和第二伪栅极层中的每一个图案化成多个第一伪栅极堆叠和多个第二伪栅极堆叠，其中第一伪栅极堆叠分别更宽 沿栅极长度方向比每个第二虚拟栅极叠层，其中使用导致第一和第二伪栅极层之间的不同横向修整的反应离子蚀刻（RIE）工艺来执行图案化。

公开(公告)号：US09530669B1

公开(公告)日：2016-12-27

申请号：US14954051

申请日：2015-11-30

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/762 ,  H01L21/3205 ,  H01L21/308 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L31/18 ,  H01L21/28

CPC classification number: H01L21/02694 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28255 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7378 ,  H01L29/7848 ,  H01L29/785 ,  H01L31/1816 ,  H01L2924/10271

Abstract: A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.

Abstract translation: 一种半导体器件，包括具有从所述衬底表面突出的区域的衬底; 布置在该区域上的松弛半导体; 设置在松弛半导体上的附加半导体; 和低密度电介质设置在松弛半导体之下且至少部分地位于衬底的突出区域附近。

公开(公告)号：US20160372552A1

公开(公告)日：2016-12-22

申请号：US14745666

申请日：2015-06-22

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/15 ,  H01L29/165 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L29/1054 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L23/3677 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/157 ,  H01L29/165 ,  H01L29/785 ,  H01L2029/7858

Abstract: A structure includes a substrate and a strain relaxed buffer (SRB) that has a bottom surface disposed on the substrate and an opposite top surface. The SRB is formed to have a plurality of pairs of layers, where a given pair of layers is composed of a layer of Sil−xGex and a layer of Si. The structure further includes a plurality of transistor devices formed above the top surface of the SRB and at least one contact disposed vertically through the top surface of the SRB and partially through a thickness of the SRB. The at least one contact is thermally coupled to at least one of the plurality of the Si layers for conducting heat out of the SRB via the at least one of the plurality of Si layers. A method to form the structure is also disclosed.

Abstract translation: 一种结构包括具有设置在基板上的底面和相对顶面的基板和应变缓和缓冲器（SRB）。 SRB形成为具有多对层，其中给定的一对层由Sil-xGex层和Si层组成。 该结构还包括形成在SRB的顶表面上方的多个晶体管器件以及垂直设置在SRB的顶表面上并且部分地穿过SRB的厚度的至少一个触点。 所述至少一个接触件热耦合到所述多个Si层中的至少一个，以通过所述多个Si层中的所述至少一个将所述SRB传导出所述SRB。 还公开了形成该结构的方法。