公开(公告)号：US09773841B2

公开(公告)日：2017-09-26

申请号：US15056548

申请日：2016-02-29

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L29/06 ,  H01L27/24 ,  H01L27/1158 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11553 ,  H01L45/00

CPC classification number: H01L27/2454 ,  H01L27/11553 ,  H01L27/1158 ,  H01L27/2481 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/1608

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

公开(公告)号：US20170117292A1

公开(公告)日：2017-04-27

申请号：US15397919

申请日：2017-01-04

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  G11C13/0007 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/52 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/249 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

公开(公告)号：US09564471B2

公开(公告)日：2017-02-07

申请号：US15095208

申请日：2016-04-11

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L27/08 ,  H01L27/24 ,  H01L27/10 ,  H01L23/52 ,  G11C13/00 ,  H01L23/528 ,  H01L27/115 ,  H01L45/00

CPC classification number: H01L27/11582 ,  G11C13/0007 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/52 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/249 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

Abstract translation: 形成电路部件的方法包括形成水平延伸和垂直重叠特征的堆叠。 堆叠具有主要部分和端部。 至少一些特征在末端部分中更深地移动到堆叠中的端部中在水平方向上延伸得更远。 操作结构通过主要部分的特征垂直地形成，并且虚拟结构通过端部中的特征垂直地形成。 通过特征形成水平细长的开口以从特征的材料形成水平细长的和垂直重叠的线。 这些线分别从主要部分延伸到端部，并且单独地横向地围绕操作结构和虚拟结构的垂直延伸部分的侧面。 至少部分地，在水平伸长的开口之间的主要端部和端部中部分地去除在线之间高度的牺牲材料。 公开了其他方面和实现。

公开(公告)号：US09536618B2

公开(公告)日：2017-01-03

申请号：US14746416

申请日：2015-06-22

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurielo Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/32 ,  G11C16/16 ,  G11C16/06 ,  G11C16/04 ,  G11C16/08 ,  G11C8/08

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

公开(公告)号：US09396791B2

公开(公告)日：2016-07-19

申请号：US14334946

申请日：2014-07-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shyam Sunder Raghunathan ,  Pranav Kalavade ,  Krishna K. Parat ,  Charan Srinivasan

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3427

Abstract: Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal.

Abstract translation: 提供了用于编程具有多级通过信号的存储器的存储器和方法。 一种方法包括将选择要编程的存储器的单元编程为存储器的特定目标数据状态，使用程序干扰来编程选择要编程的存储器的单元，以在编程期间将目标数据状态低于特定目标数据状态 将存储器的单元选择为被编程到特定目标数据状态，以及将选择要编程的存储器的单元的通道电压提升到低于特定目标数据状态的目标数据状态。 升压可能包括使用多步通过信号。

公开(公告)号：US20160133638A1

公开(公告)日：2016-05-12

申请号：US14536021

申请日：2014-11-07

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat ,  Luan C. Tran ,  Meng-Wei Kuo ,  Yushi Hu

IPC: H01L27/115

CPC classification number: H01L27/11524 ,  H01L21/8221 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

Abstract translation: 一些实施例包括具有源材料，源材料上方的介电材料，介电材料上方的选择栅极材料，选择栅极材料上方的存储单元堆叠，位于介电材料的开口中的导电插塞的装置和方法，以及 接触源材料的一部分，以及延伸穿过存储单元堆叠和选择栅极材料并与导电插塞接触的沟道材料。

公开(公告)号：US09276011B2

公开(公告)日：2016-03-01

申请号：US13838579

申请日：2013-03-15

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/2454 ,  H01L27/11553 ,  H01L27/1158 ,  H01L27/2481 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/1608

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

Abstract translation: 各种实施例包括诸如具有连续单元柱的存储器堆叠的装置和方法。 在各种实施例中，该装置包括源材料，缓冲材料，选择栅极漏极（SGD）以及布置在源材料和SGD之间的存储堆叠。 存储器堆叠包括交替电平的导体材料和电介质材料。 连续的通道填充材料形成从源材料连续到至少与SGD相对应的水平的细胞柱。

公开(公告)号：US09184175B2

公开(公告)日：2015-11-10

申请号：US13838297

申请日：2013-03-15

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract translation: 垂直存储器中的浮动存储单元。 控制栅极形成在介电材料的第一层和第二层电介质材料之间。 浮动栅极形成在介电材料的第一层和第二层介质材料之间，其中浮动栅极包括朝向控制栅极延伸的突起。 在浮置栅极和控制栅极之间形成电荷阻挡结构，其中电荷阻挡结构的至少一部分围绕突起卷绕。

公开(公告)号：US20140264533A1

公开(公告)日：2014-09-18

申请号：US13838579

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/115

CPC classification number: H01L27/2454 ,  H01L27/11553 ,  H01L27/1158 ,  H01L27/2481 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/1608

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

Abstract translation: 各种实施例包括诸如具有连续单元柱的存储器堆叠的装置和方法。 在各种实施例中，该装置包括源材料，缓冲材料，选择栅极漏极（SGD）以及布置在源材料和SGD之间的存储器堆叠。 存储器堆叠包括交替电平的导体材料和电介质材料。 连续的通道填充材料形成从源材料连续到至少与SGD相对应的水平的细胞柱。

公开(公告)号：US20140264532A1

公开(公告)日：2014-09-18

申请号：US13838297

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L29/788

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract translation: 垂直存储器中的浮动存储单元。 控制栅极形成在介电材料的第一层和第二层电介质材料之间。 浮动栅极形成在介电材料的第一层和第二层介质材料之间，其中浮动栅极包括朝向控制栅极延伸的突起。 在浮置栅极和控制栅极之间形成电荷阻挡结构，其中电荷阻挡结构的至少一部分围绕突起卷绕。