利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

245 条记录 (耗时 0.03 秒)

    Memory system, semiconductor memory device and method of driving same
    72.
    发明授权
    Memory system, semiconductor memory device and method of driving same 有权
    存储器系统，半导体存储器件及其驱动方法

    公开(公告)号：US07558141B2

    公开(公告)日：2009-07-07

    申请号：US11955900

    申请日：2007-12-13

    申请人： Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Masaru Kito ,  Hideaki Aochi ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

    发明人： Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Masaru Kito ,  Hideaki Aochi ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

    IPC分类号： G11C7/14

    CPC分类号： H01L27/115 ,  G11C7/18 ,  G11C8/08 ,  H01L27/11526 ,  H01L27/11529

    摘要： A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select transistors, a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function, second dummy transistors formed above said memory cell transistors, and second select transistors formed above said second dummy transistors; wherein a first potential is provided to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of write operation to write data to said memory cell transistors.

    摘要翻译： 半导体存储器件具有半导体衬底，形成在所述半导体衬底的表面上的第一选择晶体管，形成在所述第一选择晶体管上方的第一虚拟晶体管，形成在所述第一虚拟晶体管上方的多个存储单元晶体管， 垂直于所述半导体衬底的表面，每个所述存储单元晶体管包括具有电荷累积功能的绝缘层，形成在所述存储单元晶体管上方的第二虚拟晶体管以及形成在所述第二虚设晶体管上方的第二选择晶体管; 其中第一电位被提供给所述第一选择晶体管的栅电极和所述第一虚拟晶体管的栅电极，并且第二电位被提供给所述第二选择晶体管的栅电极和所述第二虚晶体管的栅电极 写入操作的时间将数据写入到所述存储单元晶体管。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE
    73.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE 有权
    用于制造半导体存储器件的半导体存储器件和方法

    公开(公告)号：US20090146190A1

    公开(公告)日：2009-06-11

    申请号：US12325711

    申请日：2008-12-01

    申请人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

    发明人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L27/11578 ,  H01L27/11575 ,  H01L27/11582

    摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device, comprising a plurality of memory strings, each of the memory strings being constituted with a plurality of electrically erasable memory cells being serially connected each other, the memory strings comprising: a columnar semiconductor layer perpendicularly extending toward a substrate; a plurality of conductive layers being formed in parallel to the substrate and including a first space between a sidewall of the columnar semiconductor layers; and characteristic change layer being formed on the sidewall of the columnar semiconductor layer faced to the first space or a sidewall of the conductive layer faced to the first space and changing characteristics accompanying with applied voltage; wherein the plurality of the conductive layers have a function of a relative movement to a prescribed direction for the columnar semiconductor layer.

    摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括多个存储器串，每个存储器串由多个电可擦除存储器单元组成，所述多个电可擦除存储器单元串联连接，所述存储器串包括 ：向衬底垂直延伸的柱状半导体层; 多个导电层平行于衬底形成并且包括柱状半导体层的侧壁之间的第一空间; 并且特征变化层形成在面向面向第一空间的导电层的第一空间或侧壁的柱状半导体层的侧壁上，并且伴随施加电压的变化特性; 其中所述多个所述导电层具有对于所述柱状半导体层相对于规定方向的相对移动的功能。

    Nonvolatile semiconductor memory device and method of manufacturing the same
    78.
    发明授权
    Nonvolatile semiconductor memory device and method of manufacturing the same 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US08569133B2

    公开(公告)日：2013-10-29

    申请号：US13366509

    申请日：2012-02-06

    申请人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

    发明人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

    摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.

    摘要翻译： 非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。 每个存储器串都具有第一半导体层，该第一半导体层具有相对于基板在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。