公开(公告)号：US12087632B2

公开(公告)日：2024-09-10

申请号：US17542787

申请日：2021-12-06

Applicant: Micron Technology, Inc.

Inventor： Corey Staller ,  Anilkumar Chandolu

IPC: H01L21/02 ,  H01L21/8234 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/823412 ,  H01L21/02112 ,  H01L21/02225 ,  H01L21/02282 ,  H01L21/02321 ,  H01L21/02343 ,  H01L21/823437 ,  H10B41/27 ,  H10B43/27

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. A stair-step structure is formed into the stack. A first liquid is applied onto the stair-step structure. The first liquid comprises insulative physical objects that individually have at least one of a maximum submicron dimension or a minimum submicron dimension. The first liquid is removed to leave the insulative physical objects touching one another and to have void-spaces among the touching insulative physical objects. A second liquid that is different from the first liquid is applied into the void-spaces. The second liquid is changed into a solid insulative material in the void-spaces. Other embodiments, including structure, are disclosed.

公开(公告)号：US12041775B2

公开(公告)日：2024-07-16

申请号：US17933227

申请日：2022-09-19

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Tom J. John ,  Darwin A. Clampitt ,  Anilkumar Chandolu ,  Prakash Rau Mokhna Rau ,  Christopher J. Larsen ,  Kye Hyun Baek

IPC: H10B43/27 ,  H01L21/768

CPC classification number: H10B43/27 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

公开(公告)号：US20240099006A1

公开(公告)日：2024-03-21

申请号：US18525597

申请日：2023-11-30

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  Anilkumar Chandolu ,  S M Istiaque Hossain

IPC: H10B43/27 ,  G11C11/56 ,  H01L21/768

CPC classification number: H10B43/27 ,  G11C11/5671 ,  H01L21/76879 ,  H01L21/76897

Abstract: An electronic device comprises a stack structure comprising vertically alternating insulative structures and conductive structures arranged in tiers, pillars extending vertically through the stack structure, and a barrier material overlying the stack structure. The electronic device comprises a first insulative material extending through the barrier material and into an upper tier portion of the stack structure, and a second insulative material laterally adjacent to the first insulative material and laterally adjacent to at least some of the conductive structures in the upper tier portion of the stack structure. At least a portion of the second insulative material is in vertical alignment with the barrier material. Additional electronic devices and related methods and systems are also disclosed.

公开(公告)号：US20240015969A1

公开(公告)日：2024-01-11

申请号：US18371099

申请日：2023-09-21

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: Some embodiments include a method of forming an integrated assembly. Laterally alternating first and second sacrificial materials are formed over a conductive structure, and then a stack of vertically alternating first and second levels is formed over the sacrificial materials. The first levels include first material and the second levels include insulative second material. Channel-material-openings are formed to extend through the stack and through at least some of the strips. Channel-material-pillars are formed within the channel-material-openings. Slits are formed to extend through the stack and through the sacrificial materials. The first sacrificial material is replaced with first conductive material and then the second sacrificial material is replaced with second conductive material. At least some of the first material of the stack is replaced with third conductive material. Some embodiments include integrated assemblies.

公开(公告)号：US11871575B2

公开(公告)日：2024-01-09

申请号：US17806829

申请日：2022-06-14

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Christopher J. Larsen ,  Anilkumar Chandolu ,  Wesley O. McKinsey ,  Tom J. John ,  Arun Kumar Dhayalan ,  Prakash Rau Mokhna Rau

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/20

CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/20

Abstract: An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

公开(公告)号：US11800711B2

公开(公告)日：2023-10-24

申请号：US17322246

申请日：2021-05-17

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H01L27/11582 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: Some embodiments include a method of forming an integrated assembly. Laterally alternating first and second sacrificial materials are formed over a conductive structure, and then a stack of vertically alternating first and second levels is formed over the sacrificial materials. The first levels include first material and the second levels include insulative second material. Channel-material-openings are formed to extend through the stack and through at least some of the strips. Channel-material-pillars are formed within the channel-material-openings. Slits are formed to extend through the stack and through the sacrificial materials. The first sacrificial material is replaced with first conductive material and then the second sacrificial material is replaced with second conductive material. At least some of the first material of the stack is replaced with third conductive material. Some embodiments include integrated assemblies.

公开(公告)号：US11705385B2

公开(公告)日：2023-07-18

申请号：US17367990

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： Indra V. Chary ,  Chet E. Carter ,  Anilkumar Chandolu ,  Justin B. Dorhout ,  Jun Fang ,  Matthew J. King ,  Brett D. Lowe ,  Matthew Park ,  Justin D. Shepherdson

IPC: H01L23/48 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/28 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27

CPC classification number: H01L23/481 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/76897 ,  H01L29/40117 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27

Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

公开(公告)号：US20230117100A1

公开(公告)日：2023-04-20

申请号：US18083991

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lise M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H10B43/27 ,  H01L23/528 ,  H10B43/10 ,  H01L23/522 ,  H01L21/02 ,  H10B51/20 ,  H01L21/67

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US20230045353A1

公开(公告)日：2023-02-09

申请号：US17396939

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Indra V. Chary ,  Anilkumar Chandolu ,  Sidhartha Gupta ,  Shuangqiang Luo

IPC: H01L23/528 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11524 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A microelectronic device, including a stack structure including alternating conductive structures and dielectric structures is disclosed. Memory pillars extend through the stack structure. Contacts are laterally adjacent to the memory pillars and extending through the stack structure. The contacts including active contacts and support contacts. The active contacts including a liner and a conductive material. The support contacts including the liner and a dielectric material. The conductive material of the active contacts is in electrical communication with the memory pillars. Methods and electronic systems are also disclosed.

公开(公告)号：US11532638B2

公开(公告)日：2022-12-20

申请号：US17008130

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11597 ,  H01L21/02 ,  H01L21/67 ,  G11C16/04

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.