公开(公告)号：US20170250313A1

公开(公告)日：2017-08-31

申请号：US15594392

申请日：2017-05-12

Applicant: Micron Technology, Inc.

Inventor： Martin F. Schubert ,  Vladimir Odnoblyudov ,  Lifang Xu

IPC: H01L33/38 ,  H01L33/32 ,  H01L33/56 ,  H01L33/42 ,  H01L33/40 ,  H01L33/50 ,  H01L33/06 ,  H01L33/30

Abstract: Solid-state radiation transducer (SSRT) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed herein. An SSRT device configured in accordance with a particular embodiment can include a radiation transducer including a first semiconductor material, a second semiconductor material, and an active region between the first semiconductor material and the second semiconductor material. The SSRT device can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. The second contact can include a plurality of buried-contact elements electrically coupled to the second semiconductor material. Individual buried-contact elements can have a transparent portion directly adjacent to the second semiconductor material. The second contact can further include a base portion extending between the buried-contact elements, such as a base portion that is least partially planar and reflective.

公开(公告)号：US20160254412A1

公开(公告)日：2016-09-01

申请号：US15149740

申请日：2016-05-09

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Scott D. Schellhammer ,  Shan Ming Mou ,  Michael J. Bernhardt

IPC: H01L33/38 ,  H01L33/58 ,  H01L33/42

CPC classification number: H01L33/38 ,  H01L31/02168 ,  H01L31/0236 ,  H01L31/02363 ,  H01L33/22 ,  H01L33/42 ,  H01L33/58 ,  H01L2933/0091 ,  Y02E10/50

Abstract: Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device.

公开(公告)号：US09041005B2

公开(公告)日：2015-05-26

申请号：US14262538

申请日：2014-04-25

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Lifang Xu ,  Scott D. Schellhammer ,  Thomas Gehrke ,  Zaiyuan Ren ,  Anton J. De Villiers

IPC: H01L33/24 ,  H01L33/06 ,  H01L33/32 ,  H01L33/22 ,  H01L33/38 ,  H01L33/40

CPC classification number: H01L33/24 ,  H01L33/06 ,  H01L33/22 ,  H01L33/32 ,  H01L33/382 ,  H01L33/405

Abstract: Solid state lighting (“SSL”) devices with cellular arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode includes a semiconductor material having a first surface and a second surface opposite the first surface. The semiconductor material has an aperture extending into the semiconductor material from the first surface. The light emitting diode also includes an active region in direct contact with the semiconductor material, and at least a portion of the active region is in the aperture of the semiconductor material.

Abstract translation: 本文公开了具有蜂窝阵列和相关制造方法的固态照明（“SSL”）设备。 在一个实施例中，发光二极管包括具有第一表面和与第一表面相对的第二表面的半导体材料。 半导体材料具有从第一表面延伸到半导体材料中的孔。 发光二极管还包括与半导体材料直接接触的有源区，并且有源区的至少一部分位于半导体材料的孔中。

公开(公告)号：US08865495B2

公开(公告)日：2014-10-21

申请号：US13897922

申请日：2013-05-20

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Zaiyuan Ren

IPC: H01L21/205 ,  H01L33/18 ,  H01L33/32 ,  H01L33/16 ,  H01L33/24 ,  H01L33/20

CPC classification number: H01L33/32 ,  H01L33/16 ,  H01L33/20 ,  H01L33/24

Abstract: Solid state lighting devices grown on semi-polar facets and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (“GaN”) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (“InGaN”)/GaN multi quantum well (“MQW”) active region directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN/GaN MQW, and P-type GaN materials is grown a semi-polar sidewall.

Abstract translation: 本文公开了在半极面上生长的固态照明装置和相关的制造方法。 在一个实施例中，固态光器件包括具有N型氮化镓（“GaN”）材料的发光二极管，与N型GaN材料间隔开的P型GaN材料和氮化铟镓（ “InGaN”）/ GaN多量子阱（“MQW”）有源区直接在N型GaN材料和P型GaN材料之间。 N型GaN，InGaN / GaN MQW和P型GaN材料中的至少一种生长为半极性侧壁。

公开(公告)号：US12127401B2

公开(公告)日：2024-10-22

申请号：US18321659

申请日：2023-05-22

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Larsen ,  Lifang Xu

IPC: H10B41/27 ,  G11C5/06 ,  H01L21/768 ,  H01L23/538 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L21/76877 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20240250024A1

公开(公告)日：2024-07-25

申请号：US18420074

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Surendranath C. Eruvuru ,  Lifang Xu

IPC: H01L23/528 ,  G11C16/04 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

Abstract: A stairless electrical interconnect structure with contact pillars embedded within and collectively accessing each tier in a periodic material stack, e.g., to provide electrical connections to access lines associated with a three-dimensional memory array, is described. The contact pillars can be formed in a corresponding array of vertical contact pillar trenches etched into the material stack in two stages to create depths of the trenches that vary between columns by a fixed number of tiers and then offset the depths between rows.

公开(公告)号：US11961801B2

公开(公告)日：2024-04-16

申请号：US17373121

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  David H. Wells ,  Harsh Narendrakumar Jain ,  Umberto Maria Meotto ,  Paolo Tessariol

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.

公开(公告)号：US20240071502A1

公开(公告)日：2024-02-29

申请号：US17822712

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Lifang Xu ,  Jordan D. Greenlee

IPC: G11C16/08 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11578

CPC classification number: G11C16/08 ,  H01L21/76843 ,  H01L21/76831 ,  H01L21/76885 ,  H01L27/1157 ,  H01L27/11578

Abstract: Methods, systems, and devices for staircase formation in a memory array are described. A first liner material may be deposited on a tread above a first contact surface and a portion of the first liner material may be doped. A second liner material may be deposited over the first liner and a portion of the second liner material may be doped. After doping the portions of the liner materials, the undoped portions of the liner materials may be removed so that the materials above a second contact surface can be at least partially removed via a first removal process. The doped portion of the first liner material may then be cut back so that a second removal process can expose the second contact surface and a third contact (while the first contact surface is protected from the removal process by the liner materials).

公开(公告)号：US20240071501A1

公开(公告)日：2024-02-29

申请号：US18364397

申请日：2023-08-02

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Umberto Maria Meotto ,  Aaron S. Yip

IPC: G11C16/04 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Microelectronic devices include a stack having a vertically alternating sequence of insulative and conductive structures arranged in tiers. Slit structures extend through the stack, dividing the stack into blocks. A first series of stadiums—within the stack of a first block of a pair of the blocks—includes at least one stadium having multiple parallel sets of staircases. A second series of stadiums—within the stack of a second block of the pair of blocks—includes at least one additional stadium having additional multiple parallel sets of staircases that are mirrored, across one of the slit structures, to the multiple parallel sets of staircases of the first series. In methods of fabrication, common mask openings are used to form the mirrored staircase profiles once stadiums are already at substantially their final depths in the stack structure. Electronic systems are also disclosed.

公开(公告)号：US20240055350A1

公开(公告)日：2024-02-15

申请号：US17819538

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Mark S. Swenson ,  Surendranath C. Eruvuru ,  Lifang Xu

IPC: H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/53295 ,  H01L21/76837

Abstract: An electronic device comprises a stack comprising an alternating sequence of conductive structures and insulative structures arranged in tiers, and at least one dielectric-filled slot extending vertically through the stack and extending in a first horizontal direction. The at least one dielectric-filled slot is defined between two internal sidewalls of the stack. The electronic device comprises additional dielectric-filled slots extending vertically through the stack and extending in a second horizontal direction transverse to the first horizontal direction, and isolation structures laterally interposed between the at least one dielectric-filled slot and the additional dielectric-filled slots. The isolation structures are laterally adjacent to the conductive structures of the stack, and at least some of the isolation structures are vertically adjacent to the insulative structures of the stack. Related systems and methods of forming the electronic devices are also disclosed.