公开(公告)号：US20060065421A1

公开(公告)日：2006-03-30

申请号：US11237856

申请日：2005-09-29

申请人： Kazumasa Arai ,  Yutaka Kubota ,  Yusuke Igarashi ,  Hidefumi Saito ,  Masami Motegi ,  Noriaki Sakamoto

发明人： Kazumasa Arai ,  Yutaka Kubota ,  Yusuke Igarashi ,  Hidefumi Saito ,  Masami Motegi ,  Noriaki Sakamoto

IPC分类号： H05K5/06

CPC分类号： H01L21/565 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49531 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/056 ,  H05K3/284 ,  H05K3/285 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2203/0315 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Warping of a hybrid integrated circuit device 10 due to shrinkage on curing of a sealing resin 14 is suppressed. The hybrid integrated circuit device 10 includes: a conductive pattern 13 provided on a surface of a circuit board 11; circuit elements 15 fixed to the conductive pattern 13; thin metal wires 17 electrically connecting the circuit elements 15 to the conductive pattern; leads 16 which are connected to the conductive pattern 13 to become output or input and extended to the outside; and a sealing resin 14 which is made of a thermosetting resin and covers the circuit board 11 by transfer molding while at least a rear surface of the circuit board is exposed. Here, a thermal expansion coefficient of the sealing resin 14 is set to be smaller than a thermal expansion coefficient of the circuit board 11. Thus, warping of the circuit board 11 in an after cure step can be prevented.

摘要翻译： 由于密封树脂14的固化收缩而导致混合集成电路装置10的翘曲被抑制。 混合集成电路装置10包括：设置在电路板11的表面上的导电图案13; 固定到导电图案13的电路元件15; 将电路元件15电连接到导电图案的细金属线17; 引线16，其连接到导电图案13以输出或输入并延伸到外部; 以及密封树脂14，其由热固性树脂制成，并且在电路板的至少后表面露出时通过传递模塑覆盖电路板11。 这里，将密封树脂14的热膨胀系数设定为小于电路基板11的热膨胀系数。 因此，可以防止在后固化步骤中的电路板11的翘曲。

公开(公告)号：US20050230801A1

公开(公告)日：2005-10-20

申请号：US11049993

申请日：2005-02-04

申请人： Hiroshi Kuroda ,  Noriaki Sakamoto ,  Takafumi Kikuchi

发明人： Hiroshi Kuroda ,  Noriaki Sakamoto ,  Takafumi Kikuchi

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L24/06 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/48 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01056 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a semiconductor device including a package board, a first DRAM that is flip-chip connected on the package board, a second DRAM that is of the same type as the first DRAM and is mounted face up on the first DRAM such that the orientation of the arrangement of the pads is at 90° from that of the first DRAM, a microcomputer chip disposed on the second DRAM, wires, and a sealing medium. The package board has a plurality of common wires for electrically connecting first electrodes for the first DRAM and second electrodes for the second DRAM. The common wires can be disposed without crossing on the surface wire layer of the package board, since the orientation of the arrangement of the pads of the second DRAM forms an angle of 90° relative to that of the first DRAM.

摘要翻译： 本发明涉及一种包括封装板的半导体器件，在封装板上连接倒装芯片的第一DRAM，与第一DRAM相同类型的第二DRAM，并面向上安装在第一DRAM上，如 焊盘的布置方向与第一DRAM的方向成90°，设置在第二DRAM上的微计算机芯片，导线和密封介质。 封装板具有用于电连接第一DRAM的第一电极和第二DRAM的第二电极的多条公共电线。 由于第二DRAM的焊盘的排列方向相对于第一DRAM的90°的角度形成角度，所以可以将普通的布线布置成不会交叉在封装板的表面布线层上。

公开(公告)号：US20050230796A1

公开(公告)日：2005-10-20

申请号：US11105482

申请日：2005-04-14

申请人： Noriaki Sakamoto ,  Takehisa Yokohama ,  Tomoru Sato ,  Takafumi Kikuchi ,  Fujio Ito

发明人： Noriaki Sakamoto ,  Takehisa Yokohama ,  Tomoru Sato ,  Takafumi Kikuchi ,  Fujio Ito

IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C29/56 ,  H01L21/822 ,  H01L23/02 ,  H01L23/31 ,  H01L23/495 ,  H01L23/544 ,  H01L25/18 ,  H01L27/04

CPC分类号： H01L24/49 ,  H01L22/34 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100, SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109) is provided at inside of ASIC 100, and SDRAM 101 is tested from outside of SDRAM 101, that is, from ASIC 100. By providing the test circuit of SDRAM 101 at inside of ASIC 100, it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.

摘要翻译： 为了提供一种测试技术，能够通过将通过将多个半导体芯片安装到单个封装构成的SIP等的半导体集成电路中的多个端子（引脚）减少到封装尺寸，在通过安装 将多个半导体芯片连接到ASIC 100，SDRAM 101等的信号封装，在ASIC 100的内部提供测试SDRAM 101（SDRAMBIST 109）的电路，并且从RAM 101的外部测试SDRAM 101， 通过在ASIC100的内部提供SDRAM 101的测试电路，不需要将用于测试SDRAM 101的终端拉伸到SIP 102的外部。

公开(公告)号：US20050230793A1

公开(公告)日：2005-10-20

申请号：US11106678

申请日：2005-04-15

申请人： Fujio Ito ,  Hiromichi Suzuki ,  Akihiko Kameoka ,  Noriaki Sakamoto

发明人： Fujio Ito ,  Hiromichi Suzuki ,  Akihiko Kameoka ,  Noriaki Sakamoto

IPC分类号： H01L21/60 ,  H01L21/48 ,  H01L21/607 ,  H01L23/495 ,  H01L23/50

CPC分类号： H01L24/85 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/06153 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/78743 ,  H01L2224/85148 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires which connect the pads of the microcomputer chip and the inner leads and which are disposed so as to bridge over the SDRAM and are formed with loops at positions higher than loops of the first wires. An interface circuit for a memory bus is connected only between the chips, without connecting to external terminals, and is closed within a package. Therefore, pins can be utilized for other functions correspondingly and a multi-pin configuration can be achieved. Further, the cost of an SIP (semiconductor device) can be reduced owing to the adoption of a frame type.

摘要翻译： 半导体器件包括微计算机芯片，与微计算机芯片一起设置并且比微计算机芯片薄的SDRAM，多个内引线和外引线，连接微计算机芯片的焊盘和第二引线的第一引线 SDRAM和第二线，其连接微型计算机芯片的焊盘和内部引线，并布置成跨越SDRAM并且在高于第一线的环的位置处形成有环。 用于存储器总线的接口电路仅在芯片之间连接，而不连接到外部端子，并且在封装内封闭。 因此，可以相应地使用引脚用于其他功能，并且可以实现多引脚配置。 此外，由于采用帧类型，可以降低SIP（半导体器件）的成本。

公开(公告)号：US06949470B2

公开(公告)日：2005-09-27

申请号：US10664333

申请日：2003-09-17

申请人： Yusuke Igarashi ,  Hideki Mizuhara ,  Noriaki Sakamoto

发明人： Yusuke Igarashi ,  Hideki Mizuhara ,  Noriaki Sakamoto

IPC分类号： H01L23/12 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H05K1/18 ,  H05K3/06 ,  H05K3/10 ,  H05K3/20 ,  H05K3/28 ,  H01L21/302

CPC分类号： H05K3/205 ,  H01L21/566 ,  H01L23/3128 ,  H01L23/538 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/07802 ,  H01L2924/15311 ,  H05K1/185 ,  H05K1/187 ,  H05K3/062 ,  H05K3/108 ,  H05K3/284 ,  H05K2201/098 ,  Y10T29/49146 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/49171 ,  H01L2924/00014 ,  H01L2924/00

摘要： Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 formed by laminating a first conductive film 11 and a second conductive film 12 is covered with a photoresist layer PR having opening portions 13 with inclined surfaces 13S, a conductive wiring layer 14 is formed in the opening portions by electrolytic plating to form inverted inclined surfaces 14R, and then, when covering the same with the sealing resin layer 21, an anchoring effect is produced by making the sealing resin layer 21 bite into the inverted inclined surfaces 14R so as to strengthen bonding of the sealing resin layer 21 with the conductive wiring layer 14.

摘要翻译： 优选地，其中使用具有导电图案的柔性片的半导体器件作为支撑衬底，在其上安装半导体元件，并且已经开发了组合。 在这种情况下，存在无法形成多层布线结构并且在制造工艺中绝缘树脂片翘曲突出的问题。 为了解决这些问题，通过层叠第一导电膜11和第二导电膜12而形成的层叠板10被具有带有倾斜面13S的开口部13的光致抗蚀剂层PR覆盖，导电布线层14形成在 通过电解电镀形成开口部，以形成倒置的倾斜面14R，然后当用密封树脂层21覆盖时，通过使密封树脂层21咬入倒置的倾斜表面14R而产生锚定效果，以便 以加强密封树脂层21与导电布线层14的接合。

公开(公告)号：US06274895B1

公开(公告)日：2001-08-14

申请号：US09385631

申请日：1999-08-27

申请人： Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

发明人： Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

IPC分类号： H01L2710

CPC分类号： H01L27/10897 ,  G11C5/025 ,  G11C11/4097 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection via the second interconnection according to combinations with the wiring dedicated areas adjacent thereto as needed.

摘要翻译： 具有用于实现特定逻辑电路的一个至多个MOSFET的多个单位区域被放置在第一方向上。 在每个单位区域上形成沿第一方向延伸的第一互连。 沿着第一方向延伸的第二互连沿着多个单元区域和单元区域外部形成。 在相邻的单元区域之间分别设置具有沿与第一方向相交的第二方向延伸的第三互连的配线专用区域。 在每个单元区域中形成的逻辑电路具有连接到第一互连的第一连接形式和经由第二互连连接到第三互连的第二连接形式，根据需要，根据与其相邻的布线专用区域的组合。

公开(公告)号：US4932013A

公开(公告)日：1990-06-05

申请号：US187298

申请日：1988-04-28

申请人： Kunio Kojima ,  Noriaki Sakamoto ,  Toshihisa Deguchi ,  Daiji Yamane

发明人： Kunio Kojima ,  Noriaki Sakamoto ,  Toshihisa Deguchi ,  Daiji Yamane

IPC分类号： G05D3/12 ,  G11B7/085 ,  G11B21/08

CPC分类号： G11B7/08529 ,  G11B7/08505 ,  Y02P80/15

摘要： An apparatus for reading an optical disk having tracks extending tangentially includes a driving device for moving at least one light spot. A signal which indicates a deviation of the light spot from one of the tracks and a second circuit produces acceleration and deceleration signals. The driving device is controlled to accomplish a track jump of the light spot in accordance with the acceleration and deceleration signals. The second circuit produces the acceleration signal when a track jump is to be initiated and produces the deceleration signal when the ratio of the level of the tracking error signal to the peak value of the tracking error signal becomes equal to a predetermined value.

公开(公告)号：US4920528A

公开(公告)日：1990-04-24

申请号：US16258

申请日：1987-02-19

申请人： Noriaki Sakamoto ,  Yoshiki Nishioka ,  Toshihiro Yamanaka ,  Nobuyuki Horie ,  Shozou Kobayashi ,  Toshihisa Deguchi ,  Shigemi Maeda

发明人： Noriaki Sakamoto ,  Yoshiki Nishioka ,  Toshihiro Yamanaka ,  Nobuyuki Horie ,  Shozou Kobayashi ,  Toshihisa Deguchi ,  Shigemi Maeda

IPC分类号： G11B20/18

CPC分类号： G11B20/1883 ,  G11B2220/20

摘要： A disk recording method in which recording is performed on a disklike recording medium having a radially coaxial or spiral recording track that is divided into a predetermined plural number of recording sectors each acting as a recording unit. A predetermined number of dedicated sectors are provided at a rear portion of the recording track so that the contents that are recorded in defective sectors of the recording sectors are alternatively assigned to the dedicated sectors.

摘要翻译： 一种盘记录方法，其中在具有径向同轴或螺旋记录轨道的盘状记录介质上执行记录，所述盘状记录介质被分成预定的多个作为记录单元的记录扇区。 预定数量的专用扇区设置在记录轨道的后部，使得记录在记录扇区的缺陷扇区中的内容交替地分配给专用扇区。

公开(公告)号：US4840037A

公开(公告)日：1989-06-20

申请号：US153712

申请日：1988-02-08

申请人： Koji Yamada ,  Noriaki Sakamoto

发明人： Koji Yamada ,  Noriaki Sakamoto

IPC分类号： F25B5/00 ,  F25B5/02 ,  F25B13/00 ,  F25D11/00 ,  F25D17/06

CPC分类号： F25D17/062 ,  F25B5/02 ,  F25D11/006 ,  F25D2400/04

摘要： A cold-accumulation type refrigerator having variable length cycle for cooling by means of the cold-accumulation material. The cycle length is a function of refrigerator load. The refrigerator includes a refrigerating cycle to cool a refrigerator compartment and the cold-accumulation material, a load detecting device, such as a room temperature detecting device, to measure an amount of a load to be cooled, clock counting device to generate a time data, and a control device, such as microcomputer. The control device controls the operation of the refrigerator which operates in a first mode (ordinary cooling operation), a second mode wherein the refrigerator compartments are cooled by means of the cold accumulation material and a third mode wherein the cold accumulation material is cooled. The control device controls the time period for second and third mode operation as a function of load to be cooled.

摘要翻译： 一种具有可变长度循环的冷积式冷冻机，用于通过冷堆积材料进行冷却。 循环长度是冰箱负荷的函数。 冰箱包括用于冷却冷藏室和冷堆积物的制冷循环，诸如室温检测装置的负载检测装置，以测量要冷却的负载量，产生时间数据的时钟计数装置 ，以及微型计算机等的控制装置。 控制装置控制在第一模式（普通冷却操作）中操作的冰箱的操作，其中冷藏室通过冷堆积材料冷却的第二模式和冷堆积材料的第三模式。 控制装置控制作为要冷却的负载的函数的第二和第三模式操作的时间段。

公开(公告)号：US4570044A

公开(公告)日：1986-02-11

申请号：US486494

申请日：1983-04-19

申请人： Toshiaki Kobayashi ,  Noriaki Sakamoto

发明人： Toshiaki Kobayashi ,  Noriaki Sakamoto

IPC分类号： G03G15/20 ,  H05B6/00

CPC分类号： G03G15/2064

摘要： An induction heating and fixing device suitable for a copying machine comprises a fixing roller, a first iron core, a second iron core, and two third iron cores. The first iron core inserted into the center of the fixing roller. The first, the second, and the third iron cores are magnetically and mechanically combined together to form a closed magnetic circuit. Magnetic blocks are provided for combining the first, the second, and the third iron cores. Each of these iron cores comprises a plurality of isolated thin silicon steel plates. At least one of the two of the third iron cores is disassembled to remove the fixing roller from the device for maintenance.

摘要翻译： 适用于复印机的感应加热和定影装置包括定影辊，第一铁芯，第二铁芯和两个第三铁芯。 第一个铁芯插入定影辊的中心。 第一，第二和第三铁芯磁和机械地组合在一起形成封闭的磁路。 提供了用于组合第一，第二和第三铁芯的磁性块。 这些铁芯中的每一个包括多个分离的薄硅钢板。 拆卸第二铁芯中的两个中的至少一个，以从维修装置中移除定影辊。