公开(公告)号：US5933733A

公开(公告)日：1999-08-03

申请号：US493004

申请日：1995-06-21

申请人： Giuseppe Ferla ,  Ferruccio Frisina

发明人： Giuseppe Ferla ,  Ferruccio Frisina

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/1095 ,  H01L21/26586

摘要： A zero thermal budget manufacturing process for a MOS-technology power device. The method comprises the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; removing the insulated gate layer from selected portions of the semiconductor material layer surface; implanting a first dopant of a second conductivity type into the selected portions of the semiconductor material layer, the insulated gate layer acting as a mask and the first dopant of the first conductivity type being implanted in a dose and with an implantation energy suitable to obtain heavily doped regions substantially aligned with the edges of the insulated gate layer; implanting a second dopant of the second conductivity type along directions at prescribed angles with respect to a direction orthogonal to the semiconductor material layer surface, the insulated gate layer acting as a mask, the second dopant being implanted in a dose and with an implantation energy suitable to obtain lightly doped channel regions extending under the insulated gate layer; and implanting a third dopant of the first conductivity type into the heavily doped regions, to form source regions substantially aligned with the edges of the insulated gate layer.

公开(公告)号：US5631476A

公开(公告)日：1997-05-20

申请号：US509956

申请日：1995-08-01

申请人： Giuseppe Ferla ,  Ferruccio Frisina

发明人： Giuseppe Ferla ,  Ferruccio Frisina

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/12 ,  H01L23/482 ,  H01L23/495 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L23/498 ,  H01L29/74

CPC分类号： H01L24/06 ,  H01L23/4824 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L29/41741 ,  H01L29/7802 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107

摘要： In a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective fraction to an overall current and including a first doped region of a first conductivity type formed in the semiconductor layer, and a second doped region of a second conductivity type formed inside the first doped region; the package comprises a plurality of pins for the external electrical and mechanical connection; the plurality of elementary functional units is composed of sub-pluralities of elementary functional units, the second doped regions of all the elementary functional units of each sub-plurality being contacted by a same respective metal plate electrically insulated from the metal plates contacting the second doped regions of all the elementary functional units of the other sub-pluralities; each of the metal plates are connected, through a respective bonding wire, to a respective pin of the package.

摘要翻译： 在MOS技术的功率器件芯片和封装组件中，MOS技术功率器件芯片包括其中集成了多个基本功能单元的半导体材料层，每个基本功能单元对整个电流贡献相应的分数，并且包括 形成在半导体层中的第一导电类型的第一掺杂区和形成在第一掺杂区内的第二导电类型的第二掺杂区; 所述包装件包括用于外部电气和机械连接的多个销; 多个基本功能单元由多个基本功能单元组成，每个子多个元件的所有基本功能单元的第二掺杂区域与与接触第二掺杂的金属板电绝缘的相同金属板接触 其他子复数的所有基本功能单元的区域; 每个金属板通过相应的接合线连接到封装的相应引脚。

公开(公告)号：US5468660A

公开(公告)日：1995-11-21

申请号：US251514

申请日：1994-05-31

申请人： Ferruccio Frisina ,  Giuseppe Ferla

发明人： Ferruccio Frisina ,  Giuseppe Ferla

IPC分类号： H01L29/73 ,  H01L21/22 ,  H01L21/322 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/07 ,  H01L27/082 ,  H01L29/732 ,  H01L29/861 ,  H01L21/77

CPC分类号： H01L27/0761 ,  H01L21/221 ,  Y10S438/904

摘要： A bipolar power device and a fast diode are formed in a single chip of semiconductor material. The chip contains a first area having high minority carrier lifetimes in which the bipolar power device is formed. The bipolar power device is therefore capable of handling high current densities. At least one second area of the device is formed with reduced minority carrier lifetimes, with a fast diode being formed in this region.

摘要翻译： 在单芯片半导体材料中形成双极功率器件和快速二极管。 芯片包含形成双极型功率器件的少数载流子寿命的第一区域。 因此，双极型功率器件能够处理高电流密度。 器件的至少一个第二区域形成为具有减少的少数载流子寿命，其中在该区域中形成快速二极管。

公开(公告)号：US5221855A

公开(公告)日：1993-06-22

申请号：US605447

申请日：1990-10-30

申请人： Giuseppe Ferla ,  Sergio Palara

发明人： Giuseppe Ferla ,  Sergio Palara

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/082 ,  H01L29/732

CPC分类号： H01L27/0248 ,  H01L27/0821

摘要： A monolithic vertical-type semiconductor power device comprises an N+ type substrate 1 over which there is superimposed an N- type epitaxial layer 2 in which there is obtained a P type isolation pocket 3. The pocket 3 contains N type regions 4, 15 and P type regions 6 which in turn contain N+ type regions 11, 12 and P type regions 7, 9, 10 which define circuit components of the device. Isolation pocket 3 is wholly covered by a first metallisation 21 connect to ground. The metallisation 21 is in turn protected by a layer of insulating material 18 suitable for allowing the crossing of metal tracks or of a second metallisation for the connection of the different components.

公开(公告)号：US5141883A

公开(公告)日：1992-08-25

申请号：US632485

申请日：1990-12-24

申请人： Giuseppe Ferla ,  Carmelo Magro ,  Paolo Lanza

发明人： Giuseppe Ferla ,  Carmelo Magro ,  Paolo Lanza

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/7802 ,  H01L29/456 ,  H01L29/4933 ,  Y10S148/126

摘要： A process for the manufacture of power-MOS semiconductor devices achieves high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall.

公开(公告)号：US4881117A

公开(公告)日：1989-11-14

申请号：US582793

申请日：1984-02-23

申请人： Luciano Gandolfi ,  Giuseppe Ferla

发明人： Luciano Gandolfi ,  Giuseppe Ferla

IPC分类号： H01L25/18 ,  H01L23/48 ,  H01L23/52 ,  H01L25/04 ,  H01L25/07

CPC分类号： H01L24/72 ,  H01L23/52 ,  H01L25/072 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/19043

摘要： A multiplicity of semiconductor chips constituting the active elements of a semiconductor power device are attached, in a predetermined configuration, to a metal plate which acts as both a support and a first electrical terminal. Two other electrical terminals are formed by two metal electrodes having an interdigitated structure with the fingers of one electrode being inserted between those of the other electrode and which are positioned above the semiconductor chips and have tabs for establishing a connection between the electrodes and the two contact areas of each chip.

摘要翻译： 构成半导体功率器件的有源元件的多个半导体芯片以预定的配置被附接到充当支撑体和第一电气端子的金属板。 另外两个电端子由具有交叉指状结构的两个金属电极形成，一个电极的指状物插在另一个电极的指状物之间，并且位于半导体芯片之上，并且具有用于在电极和两个触点之间建立连接的突片 每个芯片的区域。

公开(公告)号：US4310571A

公开(公告)日：1982-01-12

申请号：US34204

申请日：1979-04-27

申请人： Vincenzo Daniele ,  Giuseppe Corda ,  Andrea Ravaglia ,  Giuseppe Ferla

发明人： Vincenzo Daniele ,  Giuseppe Corda ,  Andrea Ravaglia ,  Giuseppe Ferla

IPC分类号： H01C17/24 ,  H01L21/02 ,  H01L21/033 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01C17/06

CPC分类号： H01L28/20 ,  H01L21/033 ,  Y10T29/49082 ,  Y10T29/49099

摘要： Filiform elements of predetermined resistivity, e.g. selectively destructible leads of an electrically programmable read-only memory, are formed on a semiconductor substrate such as a silicon body by first depositing thereon a layer of dielectric material such as SiO.sub.2 and topping that layer with a conductive or nonconductive coating which is resistant to a chemical such as hydrofluoric acid capable of attacking the dielectric layer. Next, the top coating is partly destroyed by photolithographic treatment to leave at least one substantially rectangular patch. Thereafter, the dielectric layer is isotropically attacked by the aforementioned chemical with resulting reduction to about half its original thickness and concurrent lateral erosion of a patch-supporting pedestal of that layer whereby channels of generally semicylindrical concavity are formed around the periphery of this pedestal. The patch, if composed of conductive or semiconductive material, is then clad in an insulating envelope whereupon the dielectric layer and the patch are covered with a deposit of the desired electrical conductivity which could consist of doped polycrystalline silicon or of metal. Finally, this deposit is removed by chemical or ionic etching except in the channels of the pedestal and along a pair of parallel strips adjoining opposite pedestal sides whereby these strips remain electrically interconnected by filiform inserts left in the undercuts of the other two sides.

摘要翻译： 预定电阻率的丝状元素，例如 通过首先在诸如硅体的半导体衬底上沉积介电材料层（例如SiO 2）形成电可编程只读存储器的选择性可破坏的引线，并用导电或非导电涂层将该层顶起来，该导电或非导电涂层对 化学物质如能够侵蚀电介质层的氢氟酸。 接下来，通过光刻处理部分地破坏顶部涂层以留下至少一个基本上矩形的贴片。 此后，电介质层被上述化学物质各向同性地侵蚀，从而将其降低到其原始厚度的大约一半，并且该层的贴片支撑基座的同时横向侵蚀，从而在该基座的周边周围形成大致半圆柱形凹陷的通道。 如果由导电材料或半导体材料组成，则贴片被覆在绝缘包层中，由介电层和贴片用可掺杂多晶硅或金属的所需电导率的沉积物覆盖。 最后，通过化学或离子蚀刻除去基座的通道以及邻接相对的基座侧的一对平行条，除去这些沉积物，由此这些条通过留在另外两边的底切部中的丝状插入物而保持电互连。