公开(公告)号：US20170062120A1

公开(公告)日：2017-03-02

申请号：US14841132

申请日：2015-08-31

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Daeik Daniel Kim ,  David Francis Berdy ,  Je-Hsiung Jeffrey Lan ,  Jonghae Kim ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka

IPC: H01F27/28 ,  H01F41/14 ,  H01F41/04 ,  H01F27/245

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/245 ,  H01F41/042 ,  H01F41/046 ,  H01F41/14 ,  H01F41/32 ,  H01F2027/2809 ,  H01L23/645 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/165 ,  H01L2924/00012

Abstract: A substrate includes a first dielectric layer, a magnetic core at least partially in the first dielectric layer, where the magnetic core comprises a first non-horizontal thin film magnetic (TFM) layer. The substrate also includes a first inductor that includes a plurality of first interconnects, where the first inductor is positioned in the substrate to at least partially surround the magnetic core. The magnetic core may further include a second non-horizontal thin film magnetic (TFM) layer. The magnetic core may further include a core layer. The magnetic core may further include a third thin film magnetic (TFM) layer, and a fourth thin film magnetic (TFM) layer that is substantially parallel to the third thin film magnetic (TFM) layer.

Abstract translation: 衬底包括第一介电层，至少部分地在第一介电层中的磁芯，其中磁芯包括第一非水平薄膜磁性（TFM）层。 衬底还包括包括多个第一互连件的第一电感器，其中第一电感器定位在衬底中以至少部分地围绕磁芯。 磁芯还可以包括第二非水平薄膜磁性（TFM）层。 磁芯还可以包括芯层。 磁芯还可以包括第三薄膜磁性（TFM）层和基本上平行于第三薄膜磁性（TFM）层的第四薄膜磁性（TFM）层。

公开(公告)号：US20160358709A1

公开(公告)日：2016-12-08

申请号：US15242007

申请日：2016-08-19

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Xiangdong Zhang ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01F41/04 ,  H01F27/28

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H01F41/042 ,  H01F2017/0053 ,  H01F2017/0073 ,  H01F2027/2809

Abstract: A method includes forming a first conductive spiral and a second conductive spiral of a spiral inductor coupled to a substrate. The second conductive spiral overlays the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate. The second thickness is greater than the first thickness. The portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.

Abstract translation: 一种方法包括形成耦合到衬底的螺旋电感器的第一导电螺旋和第二导电螺旋。 第二导电螺旋覆盖第一导电螺旋。 螺旋电感器的最内圈的第一部分在垂直于衬底的方向上具有第一厚度。 最内圈的第一部分包括第一导电螺旋的第一部分，并且不包括第二导电螺旋。 最内圈的第二部分包括第二导电螺旋的第一部分。 螺旋电感器的最外圈的一部分在垂直于衬底的方向上具有第二厚度。 第二厚度大于第一厚度。 最外圈的部分包括第一导电螺旋的第二部分和第二导电螺旋的第二部分。

公开(公告)号：US09431510B2

公开(公告)日：2016-08-30

申请号：US14554718

申请日：2014-11-26

Applicant: QUALCOMM Incorporated

Inventor： Changhan Yun ,  Chengjie Zuo ,  Chi Shun Lo ,  Jonghae Kim ,  Mario F. Velez

IPC: H01L21/20 ,  H01L29/66 ,  H01G4/33 ,  H01L49/02 ,  H01G4/12

CPC classification number: H01L29/66174 ,  H01G4/1272 ,  H01G4/33 ,  H01L28/40 ,  H01L28/75

Abstract: Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.

Abstract translation: 提供了用于高Q装置的金属半导体晶片接合的方法和装置。 示例性电容器包括形成在玻璃基板，第二板和介电层上的第一板。 在第一板和玻璃基板之间不使用有机粘合剂，并且电介质层可以是本征半导体。 重掺杂的非本征半导体层接触电介质层。 电介质和非本征半导体层夹在第一和第二板之间。 在第一板和电介质层之间形成金属间层。 金属间化合物层被热压接合到第一板和电介质层。 电容器可以作为高Q电容器和/或变容二极管耦合在电路中，并且可以与移动设备集成。

公开(公告)号：US09362218B2

公开(公告)日：2016-06-07

申请号：US13968627

申请日：2013-08-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L23/498 ,  H01L21/768 ,  H01L49/02 ,  H01L23/50 ,  H01L23/64 ,  H01L23/522

CPC classification number: H01L23/49827 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/642 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/16225 ,  H01L2225/06572 ,  H01L2924/19105

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract translation: 一些新颖的特征涉及一种半导体器件，其包括衬底，穿过衬底的第一腔体。 第一腔被配置为被互连材料（例如，焊球）占据。 衬底还包括耦合到第一腔的第一侧壁的第一金属层。 衬底还包括在衬底的第一表面上的第一集成无源器件（IPD），第一IPD耦合到第一金属层。 在一些实施方案中，基底是玻璃基底。 在一些实现中，第一IPD是至少一个电容器，电感器和/或电阻器中的一个。 在一些实施方式中，半导体器件还包括在衬底的第二表面上的第二集成无源器件（IPD）。 第二IPD耦合到第一金属层。

公开(公告)号：US20160095208A1

公开(公告)日：2016-03-31

申请号：US14498230

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Je-Hsiung Jeffrey Lan ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  David Francis Berdy

IPC: H05K1/02 ,  H01L21/768 ,  H05K1/09 ,  C23F1/02 ,  H05K1/03

CPC classification number: H05K1/0271 ,  C23F1/02 ,  H01L21/768 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/09 ,  H05K2201/0154 ,  H05K2201/0195 ,  H01L2924/00

Abstract: A device includes a stress relief region between at least two stress domains of a substrate (e.g., of a semiconductor die or other integrated circuit). The stress relief region includes a conductive structure electrically coupling circuitries of the stress domains between which the conductive structure is disposed.

Abstract translation: 器件包括在衬底（例如，半导体管芯或其他集成电路）的至少两个应力结构域之间的应力消除区域。 应力消除区域包括导电结构，电耦合应力区域的电路，导电结构设置在该应力区域之间。

公开(公告)号：US20160093750A1

公开(公告)日：2016-03-31

申请号：US14498359

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Chengjie Zuo ,  Sang-June Park ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  David Francis Berdy ,  Matthew Michael Nowak ,  Robert Paul Mikulka

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/94

Abstract: An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.

Abstract translation: 一种装置包括具有位于衬底的第一侧上的第一接触的变容二极管。 变容二极管包括位于衬底的第二侧上的第二接触件，第二侧面与第一侧相对。 该装置还包括在第一触点和第二触点之间的信号路径。

公开(公告)号：US09202789B2

公开(公告)日：2015-12-01

申请号：US14254764

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak ,  Chengjie Zuo ,  Changhan Hobie Yun ,  David Francis Berdy ,  Robert Paul Mikulka

IPC: H01L23/48 ,  H01L23/552 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/04 ,  H01L23/538 ,  H05K9/00

CPC classification number: H01L23/552 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/32 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01R12/7076 ,  H01R12/714 ,  H05K1/181 ,  H05K9/0032 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.

Abstract translation: 一些新颖特征涉及包括封装衬底，管芯，封装层和第一组金属层的集成器件封装（例如管芯封装）。 封装衬底包括第一表面和第二表面。 模具耦合到封装衬底的第一表面。 封装层封装模具。 第一组金属层耦合到封装层的第一外表面。 在一些实施方案中，第一组金属层被配置为作为集成器件封装的管芯到线连接器工作。 在一些实施方案中，集成器件封装包括耦合到封装衬底的第二表面的第二组金属层。 在一些实施方案中，集成器件封装包括耦合到封装层的第二外表面的第二组金属层。

公开(公告)号：US20150304059A1

公开(公告)日：2015-10-22

申请号：US14682023

申请日：2015-04-08

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik Daniel Kim ,  David Francis Berdy ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Robert Paul Mikulka ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak ,  Ryan Scott C. Spring ,  Xiangdong Zhang

IPC: H04J1/08

CPC classification number: H04J1/08 ,  H03H7/465 ,  H03H2240/00 ,  H03H2250/00 ,  H04B1/0057 ,  H04B1/006 ,  H04B1/0064

Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.

Abstract translation: 公开了一种装置，其包括耦合到输入节点并经配置以经由输入节点接收输入信号的频率复用器电路。 频率复用器电路包括第一滤波器电路，第二滤波器电路和第三滤波器电路。 该装置还包括可配置为将第一滤波器电路的第一输出，第二滤波器电路的第二输出或第三滤波器电路的第三输出中的至少两个耦合到单个输出端口的开关电路。

公开(公告)号：US20150237732A1

公开(公告)日：2015-08-20

申请号：US14200684

申请日：2014-03-07

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco Velez ,  Daeik Daniel Kim ,  Young Kyu Song ,  Xiaonan Zhang ,  Jonghae Kim ,  Changhan Hobie Yun ,  Chengjie Zuo

IPC: H05K1/18 ,  H01L21/48 ,  H05K3/40 ,  H05K1/03 ,  H05K1/16 ,  H01L23/498 ,  H05K1/11

CPC classification number: H05K1/182 ,  H01F17/0006 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/10 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/165 ,  H05K3/4038 ,  H05K2201/10015 ,  H05K2201/10242 ,  H05K2201/10984 ,  Y10T29/49165

Abstract: A low-profile passive-on-package is provided that includes a plurality of recesses that receive corresponding interconnects. Because of the receipt of the interconnects in the recesses, the passive-on-package has a height that is less than a sum of a thickness for the substrate and an interconnect height or diameter.

Abstract translation: 提供了一种低调无源封装，其包括接收相应互连的多个凹槽。 由于在凹槽中接收到互连，所以被动封装的高度小于衬底的厚度和互连高度或直径的总和。

公开(公告)号：US20150130579A1

公开(公告)日：2015-05-14

申请号：US14078174

申请日：2013-11-12

Applicant: Qualcomm Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo

IPC: H01F27/28 ,  H01F41/06

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F17/02 ,  H01F41/06 ,  H01F2017/0073 ,  H01F2027/2809 ,  Y10T29/4902

Abstract: An apparatus includes a multi spiral inductor that includes a first spiral and a second spiral. The first spiral includes a first turn, a second turn, and a third turn. The first turn is adjacent to and separated from the second turn by first spacing. The second turn is adjacent to and separated from the third turn by second spacing. The first spacing is different from the second spacing.

Abstract translation: 一种装置包括多螺旋电感器，其包括第一螺旋和第二螺旋。 第一个螺旋包括第一回合，第二回合和第三回合。 第一匝与第二匝相邻并且与第二匝分开。 第二匝与第三匝相邻并且与第三匝分开第二个间距。 第一间距与第二间距不同。