公开(公告)号：US20160323997A1

公开(公告)日：2016-11-03

申请号：US15206612

申请日：2016-07-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Sadamichi TAKAKUSAKI

IPC: H05K1/03 ,  H01L23/14 ,  H01L21/48 ,  H05K1/09

CPC classification number: H05K3/06 ,  C04B37/021 ,  C04B2237/34 ,  C04B2237/343 ,  C04B2237/402 ,  C04B2237/406 ,  C04B2237/407 ,  C04B2237/52 ,  C04B2237/64 ,  C04B2237/82 ,  H01L21/4807 ,  H01L21/4857 ,  H01L21/4871 ,  H01L23/142 ,  H01L23/15 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/036 ,  H05K1/056 ,  H05K1/09 ,  H05K3/0011 ,  H05K3/064 ,  H05K3/4644 ,  H05K2201/09736 ,  H01L2924/00

Abstract: A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.

公开(公告)号：US20160276772A1

公开(公告)日：2016-09-22

申请号：US14662591

申请日：2015-03-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Yusheng LIN

IPC: H01R13/415 ,  H01R43/26 ,  H01R12/58

CPC classification number: H01R43/16 ,  H01R12/585 ,  H01R13/052 ,  H01R13/415 ,  H01R43/26

Abstract: A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head. Each arm includes a curved shape and the arms together form an s-shape. A length of the s-shape is longer than the shaft diameter. An outer extremity of each arm includes a contact surface configured to electrically couple to and form a friction fit with a pin receiver. In implementations the press-fit pin has only two surfaces configured to contact an inner sidewall of the pin receiver and is configured to contact the inner sidewall at only two locations. The shaft may be a cylinder. The s-shape formed by the pair of arms is visible from a view facing a top of the press-fit pin along a direction parallel with the longest length of the shaft. Versions include a through-hole extending through the head.

Abstract translation: 用于半导体封装的压配销包括终止在头部中的轴。 一对手臂远离头部的中心。 每个臂包括弯曲的形状，并且臂一起形成s形。 s形的长度比轴的直径长。 每个臂的外部末端包括被配置为电耦合到销接收器并与销接收器形成摩擦配合的接触表面。 在实施中，压配合销仅具有两个构造成接触销接收器的内侧壁的表面，并且构造成仅在两个位置处接触内侧壁。 轴可以是圆筒。 由一对臂形成的s形状从与压配合销的顶部相对的视图可以沿着与轴的最长长度平行的方向看到。 版本包括延伸穿过头部的通孔。

公开(公告)号：US20160133533A1

公开(公告)日：2016-05-12

申请号：US14816520

申请日：2015-08-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Sadamichi TAKAKUSAKI

IPC: H01L23/14 ,  H01L23/00 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/142 ,  H01L21/76886 ,  H01L23/02 ,  H01L23/3735 ,  H01L23/492 ,  H01L23/498 ,  H01L23/5383 ,  H01L24/83 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01029 ,  H01L2924/00014

Abstract: A semiconductor package. Implementations may include a substrate including a metallic baseplate coupled with an electrically insulative layer and a plurality of metallic traces coupled to the electrically insulative layer on a surface of the electrically insulative layer opposing a surface of the electrically insulative layer coupled to the metallic baseplate. The plurality of metallic traces may include at least two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the surface of the electrically insulative layer coupled with the metallic baseplate. The package may include at least one semiconductor device coupled to the substrate, a mold compound that encapsulates the power electronic device and at least a portion of the substrate, and at least one package electrical connector coupled with the substrate.

Abstract translation: 半导体封装。 实施方案可以包括基底，其包括与电绝缘层耦合的金属基板和耦合到电绝缘层的与电绝缘层的表面相对的电绝缘层的耦合到金属基板的表面的多个金属迹线。 多个金属迹线可以包括至少两个不同的迹线厚度，其中迹线厚度是垂直于与金属基板耦合的电绝缘层的表面测量的。 封装可以包括耦合到衬底的至少一个半导体器件，封装功率电子器件和衬底的至少一部分的模具化合物，以及与衬底耦合的至少一个封装电连接器。

公开(公告)号：US20250118640A1

公开(公告)日：2025-04-10

申请号：US18987230

申请日：2024-12-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Yusheng LIN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/24 ,  H01L23/31 ,  H01L23/538 ,  H01L25/18

Abstract: Implementations of a semiconductor package may include a first substrate including a first group of leads physically coupled thereto and a second group of leads physically coupled thereto; a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and one or more semiconductor die coupled between the first substrate and the second substrate. The second group of leads may be electrically isolated from the first substrate.

公开(公告)号：US20240355638A1

公开(公告)日：2024-10-24

申请号：US18760515

申请日：2024-07-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Yusheng LIN ,  Liangbiao CHEN

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/28 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L21/4821 ,  H01L21/56 ,  H01L23/28 ,  H01L23/49534 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49861

Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

公开(公告)号：US20240332025A1

公开(公告)日：2024-10-03

申请号：US18742204

申请日：2024-06-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Yusheng LIN ,  Michael J. SEDDON ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31

CPC classification number: H01L21/302 ,  H01L21/48 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3185 ,  H01L24/04 ,  H01L24/26 ,  H01L2224/94

Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

公开(公告)号：US20240290758A1

公开(公告)日：2024-08-29

申请号：US18398499

申请日：2023-12-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/071 ,  H01L23/367 ,  H01L24/32 ,  H01L25/50 ,  H01L2224/32245

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

公开(公告)号：US20240290757A1

公开(公告)日：2024-08-29

申请号：US18174837

申请日：2023-02-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Yusheng LIN

IPC: H01L25/07 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/071 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/538 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/84 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/37012 ,  H01L2224/37147 ,  H01L2224/38 ,  H01L2224/40101 ,  H01L2224/40105 ,  H01L2224/40139 ,  H01L2224/40147 ,  H01L2224/4103 ,  H01L2224/4112 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8493

Abstract: A transistor configured for higher power can be constructed using multiple transistor dies coupled in parallel. This approach of distributing power and heat over multiple transistor dies can allow each transistor die to be made smaller, which can be helpful in improving yield. This is especially true for emerging technologies, such as silicon carbide (SiC). Power modules for power conversion may require a plurality of these multi-die transistors in a package. A package that accommodates the numerous connections required for a multi-die power module is disclosed. The package utilizes a lead frame to provide a three-dimensional sandwich structure in which multiple dies are positioned between two direct bonded copper (DBC) substrates.

公开(公告)号：US20240203846A1

公开(公告)日：2024-06-20

申请号：US18595569

申请日：2024-03-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L23/40 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/367 ,  H01L23/4093 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/80 ,  H01L25/0657

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

公开(公告)号：US20230238327A1

公开(公告)日：2023-07-27

申请号：US18193977

申请日：2023-03-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA ,  Francis J. CARNEY

IPC: H01L23/532 ,  H01L23/00

CPC classification number: H01L23/53233 ,  H01L24/33 ,  H01L24/11

Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.