利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

100 条记录 (耗时 0.04 秒)

    Electronic switch
    71.
    发明授权
    Electronic switch 失效
    电子开关

    公开(公告)号：US4612448A

    公开(公告)日：1986-09-16

    申请号：US698000

    申请日：1985-02-04

    申请人： Helmut Strack

    发明人： Helmut Strack

    IPC分类号： H03K17/687 ,  H03K17/04 ,  H03K17/567 ,  H03K17/732 ,  H03K17/72

    CPC分类号： H03K17/0406 ,  H03K17/567

    摘要： Connected in series with a thyristor (1) are two IGFETs (2, 3) one to the anode side and the other to the cathode side. Between the inner thyristor zones (6, 8) and the outer IGFET connections, a threshold circuit (10, 11) is connected to each. The threshold voltage of the threshold circuit is higher than that of the p-n junctions between the outer and adjacent inner thyristor zones (6, 7; 8, 9) including the voltage drop of the conducting IGFET. The switch is turned off by operating to turn off the IGFETs. The current then flows via the threshold elements through the two inner zones (6, 8). The charge carriers of this diode are evacuated very quickly, since carrier injection from the outer zones is no longer possible.

    摘要翻译： 与晶闸管（1）串联连接的是两个IGFET（2,3），一个连接到阳极侧，另一个连接到阴极侧。 在内部可控硅区域（6,8）和外部IGFET连接之间，连接有阈值电路（10,11）。 阈值电路的阈值电压高于包括导电IGFET的电压降的外部和相邻的内部可控硅区域（6,7; 8,9）之间的p-n结的阈值电压。 通过操作关闭开关即可关闭IGFET。 电流然后通过两个内部区域（6,8）通过阈值元件流动。 这种二极管的电荷载体被非常快地抽真空，因为从外部区域的载流子注入是不可能的。

    Insulated-gate field-effect transistor (IGFET) with injector zone
    72.
    发明授权
    Insulated-gate field-effect transistor (IGFET) with injector zone 失效
    具有注入区的绝缘栅场效应晶体管（IGFET）

    公开(公告)号：US4543596A

    公开(公告)日：1985-09-24

    申请号：US510081

    申请日：1983-06-30

    申请人： Helmut Strack ,  Jeno Tihanyi

    发明人： Helmut Strack ,  Jeno Tihanyi

    IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L29/10 ,  H01L29/73 ,  H01L29/739 ,  H01L27/02

    CPC分类号： H01L29/1095 ,  H01L29/7393 ,  H01L29/7803

    摘要： An IGFET assembly, includes a semiconductor substrate of a given first conductivity type having first and second surfaces, an IGFET having at least one channel zone of a second conductivity type opposite the first given conductivity type embedded in the first surface of the substrate, a source zone of the first conductivity type embedded planar in the channel zone, a drain zone adjacent the first surface of the substrate, a drain electrode connected to the second surface of the substrate, an insulating layer disposed on the first surface of the substrate, at least one gate electrode disposed on the insulating layer, at least one injector zone of the second conductivity type embedded in the first surface of the substrate, a contact for connecting the injector zone to a voltage source, an emitter zone of the first conductivity type embedded in the injector zone, the emitter zone having a heavier doping than the injector zone, the injector zone including a part thereof emerging to the first surface of the substrate, the drain zone having a part thereof emerging to the first surface of the substrate between the channel zone and the injector zone, the parts of the injector and drain zones emerging to the first surface of the substrate being covered by the gate electrode, and the injector zone having a surface and having a doping, at least at the surface thereof, forming a channel in the surface of the injector zone connecting the drain zone to the emitter zone when a voltage is present switching the IGFET into conduction.

    摘要翻译： IGFET组件包括具有第一和第二表面的给定第一导电类型的半导体衬底，具有至少一个第二导电类型的沟道区的IGFET，所述第二导电类型与嵌入衬底的第一表面中的第一给定导电类型相反，源极 在沟道区中嵌入平面的第一导电类型的区域，与衬底的第一表面相邻的漏极区域，连接到衬底的第二表面的漏极电极，至少设置在衬底的第一表面上的绝缘层 设置在所述绝缘层上的一个栅电极，嵌入在所述基板的第一表面中的至少一个第二导电类型的注入区，用于将所述注入区连接到电压源的接触点，所述第一导电类型的发射极区嵌入 喷射器区域，发射区具有比喷射器区域更重的掺杂，喷射器区域包括其出现到冷杉的部分 衬底的表面，排水区具有其一部分在通道区域和喷射器区域之间出现在衬底的第一表面上，出射到衬底的第一表面的喷射器和排出区域的部分被 栅电极和具有表面并且具有掺杂的注入器区域，至少在其表面处，当存在电压切换IGFET导通时，在连接漏区与发射区的喷射器区域的表面中形成通道 。

    Method of manufacturing a DMOS trench transistor
    73.
    发明授权
    Method of manufacturing a DMOS trench transistor 有权
    制造DMOS沟槽晶体管的方法

    公开(公告)号：US08415219B2

    公开(公告)日：2013-04-09

    申请号：US11638612

    申请日：2006-12-13

    申请人： Franz Hirler ,  Helmut Strack

    发明人： Franz Hirler ,  Helmut Strack

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/7813

    摘要： To attain a comparatively high breakdown voltage at a high avalanche strength and with the physical size simultaneously being as small as possible, the invention proposes constructing a transistor device in a semiconductor material region in which a first source/drain region is used as a source region and in which the source region has a comparatively reduced surface charge or surface charge density.

    摘要翻译： 为了在高雪崩强度下获得相当高的击穿电压并且物理尺寸同时尽可能小，本发明提出在其中使用第一源极/漏极区域作为源极区域的半导体材料区域中构造晶体管器件 并且其中源区具有相对减小的表面电荷或表面电荷密度。

    Component arrangement for series terminal for high-voltage applications
    76.
    发明申请
    Component arrangement for series terminal for high-voltage applications 审中-公开
    用于高压应用的串联端子的组件布置

    公开(公告)号：US20060180932A1

    公开(公告)日：2006-08-17

    申请号：US11328595

    申请日：2006-01-10

    申请人： Ralf Otremba ,  Khalil Hosseini ,  Helmut Strack

    发明人： Ralf Otremba ,  Khalil Hosseini ,  Helmut Strack

    IPC分类号： H01L23/52

    CPC分类号： H01L24/72 ,  H01L23/051 ,  H01L23/4334 ,  H01L23/49562 ,  H01L24/48 ,  H01L25/117 ,  H01L2224/48472 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： One embodiment of the invention relates to a component arrangement having a semiconductor chip, a chip carrier, a contact piece and a package. The semiconductor chip includes a first load terminal, a second load terminal and a control terminal, with the first load terminal and the second load terminal being arranged on mutually opposite sides of the semiconductor chip. The semiconductor chip is arranged on the chip carrier and is electrically and thermally conductively connected to the first load terminal. The contact piece is arranged on the second load terminal and is electrically and thermally conductively connected to it. The package is formed from a dielectric compound, which surrounds the semiconductor chip, the chip carrier and the contact piece. The chip carrier is exposed on a first side of the package, the contact piece is exposed on a second side of the package opposite the first side. A connecting leg is passed out of the package and is electrically conductively connected to the control terminal. One embodiment of the invention furthermore relates to a component cascade, in which a plurality of component arrangements are arranged on one another in the form of a stack.

    摘要翻译： 本发明的一个实施例涉及具有半导体芯片，芯片载体，接触片和封装的部件布置。 半导体芯片包括第一负载端子，第二负载端子和控制端子，其中第一负载端子和第二负载端子布置在半导体芯片的相对的相对侧上。 半导体芯片布置在芯片载体上并且电和热导电地连接到第一负载端子。 接触件布置在第二负载端子上，并且与导电连接。 封装由围绕半导体芯片，芯片载体和接触片的电介质化合物形成。 芯片载体暴露在封装的第一侧上，接触件暴露在与第一侧相对的封装的第二侧上。 连接腿从包装件中流出并与导电连接到控制端子。 本发明的一个实施例还涉及一种组件级联，其中多个组件布置以堆叠的形式彼此布置。

    High-voltage semiconductor component
    77.
    发明授权
    High-voltage semiconductor component 有权
    高压半导体元件

    公开(公告)号：US06828609B2

    公开(公告)日：2004-12-07

    申请号：US10455834

    申请日：2003-06-06

    申请人： Gerald Deboy ,  Dirk Ahlers ,  Helmut Strack ,  Michael Rueb ,  Hans Martin Weber

    发明人： Gerald Deboy ,  Dirk Ahlers ,  Helmut Strack ,  Michael Rueb ,  Hans Martin Weber

    IPC分类号： H01L2980

    CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7801 ,  H01L29/7802

    摘要： A semiconductor component having a semiconductor body comprises a blocking pn junction, a source zone of a first conductivity type and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type. The side of the zone of the second conductivity type faces the drain zone forming a first surface, and in the region between the first surface and a second surface areas of the first and second conductivity type are nested in one another. The areas of the first and second conductivity type are variably so doped that near the first surface doping atoms of the second conductivity type predominate, and near the second surface doping atoms of the first conductivity type predominate. Furthermore a plurality of floating zones of the first and second conductivity type is provided.

    摘要翻译： 具有半导体主体的半导体部件包括阻挡pn结，第一导电类型的源极区域，并且与形成与第一导电类型互补的第二导电类型的阻挡pn结的区域接合，并且第一导电类型的漏极区域 导电类型。 第二导电类型的区域侧面对排水区，形成第一表面，并且在第一表面和第一和第二导电类型的第二表面区域之间的区域彼此嵌套。 第一和第二导电类型的区域是可变地掺杂的，在第一表面附近，第二导电类型的掺杂原子占主导地位，并且在第二表面附近，第一导电类型的掺杂原子占主导地位。 此外，提供了第一和第二导电类型的多个浮动区域。

    SOI cell and method for producing it
    79.
    发明授权
    SOI cell and method for producing it 有权
    SOI电池及其制造方法

    公开(公告)号：US06225643B1

    公开(公告)日：2001-05-01

    申请号：US09158248

    申请日：1998-09-22

    申请人： Jenoe Tihanyi ,  Helmut Strack

    发明人： Jenoe Tihanyi ,  Helmut Strack

    IPC分类号： H01L2904

    CPC分类号： H01L29/7802 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396

    摘要： An SOI cell includes a semiconductor body having at least one insulator layer. A polycrystalline zone doped with a dopant of a first conductivity type is grown on the insulator layer. The polycrystalline zone is adjoined outside the region of the insulator layer by a semiconductor region, which is doped with the dopant of the first conduction type that has been diffused out of the polycrystalline zone. A dopant source having a dopant of a second conductivity type is also provided. A zone having the dopant of the second conductivity type is formed by diffusing the dopant out of the dopant source.

    摘要翻译： SOI单元包括具有至少一个绝缘体层的半导体本体。 在绝缘体层上生长掺杂有第一导电类型的掺杂剂的多晶区。 多晶区域通过半导体区域与绝缘体层的区域相邻，该半导体区域掺杂有已经扩散到多晶区域的第一导电类型的掺杂剂。 还提供了具有第二导电类型的掺杂剂的掺杂剂源。 通过将掺杂剂从掺杂剂源扩散出来，形成具有第二导电类型的掺杂剂的区域。