公开(公告)号：US09601819B2

公开(公告)日：2017-03-21

申请号：US13854948

申请日：2013-04-01

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Gerd Schuppener ,  Robert Floyd Payne

IPC: H01P3/16 ,  H01P1/04 ,  H01Q13/00 ,  H01P3/12 ,  H05K1/02

CPC classification number: H01P3/16 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01P1/04 ,  H01P3/121 ,  H01Q13/00 ,  H05K1/0239 ,  H05K1/024 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09618 ,  H05K2201/10098 ,  Y10T29/49826 ,  Y10T29/49908

Abstract: A dielectric wave guide (DWG) has a dielectric core member that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured for mating with a second DWG having a matching non-planar shaped mating end. A deformable material is disposed on the surface of the mating end of the DWG, such that when mated to a second DWG, the deformable material fills a gap region between the mating ends of the DWG and the second DWG.

公开(公告)号：US09524926B2

公开(公告)日：2016-12-20

申请号：US14848975

申请日：2015-09-09

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Juan Alejandro Herbsommer ,  Yong Lin ,  Rongwei Zhang ,  Abram Castro ,  Matthew David Romig

IPC: H01L23/49 ,  H01L23/495 ,  H01L21/288 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/2885 ,  H01L21/4821 ,  H01L21/4825 ,  H01L21/4867 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49572 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49883 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/0612 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1511 ,  H01L2924/1711 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/0665

Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

Abstract translation: 引线框架表面改性的方法包括提供至少一个预制金属引线框架或封装基板（基板）单元，其包括具有管芯焊盘和围绕管芯焊盘的多个接触区域的母材。 包括在固化步骤上形成固体的固体的材料或去除液体载体的烧结步骤的材料的油墨被加成沉积，其包括至少一个（i）芯片垫的区域 和（ii）在至少第一接触区域（第一接触区域）的一个区域。 油墨被烧结或固化以除去液体载体，使得残留基本上固体的油墨残余物。

公开(公告)号：US09515367B2

公开(公告)日：2016-12-06

申请号：US14939128

申请日：2015-11-12

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Robert Floyd Payne ,  Gerd Schuppener ,  Baher Haroun

IPC: H01P5/00 ,  H01Q13/00 ,  H01P3/16 ,  H01P5/08 ,  G02B6/44 ,  H01P11/00 ,  H01Q1/50 ,  H01Q19/10 ,  H04B1/40 ,  H01Q19/30 ,  H01P3/12 ,  H01P5/107 ,  H01P5/18

CPC classification number: H01P3/16 ,  G02B6/4416 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01P3/121 ,  H01P3/165 ,  H01P5/00 ,  H01P5/087 ,  H01P5/107 ,  H01P5/184 ,  H01P11/001 ,  H01P11/002 ,  H01Q1/50 ,  H01Q19/108 ,  H01Q19/30 ,  H04B1/40 ,  Y10T29/49016 ,  Y10T29/49826

Abstract: A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.

Abstract translation: 金属波导安装在多层基板上。 金属波导具有由顶部，底部和侧面形成的开口端，该开口端被配置为容纳电介质波导的芯构件，并且相反的锥形端通过使金属波导的顶部通过金属波导的底部下降到 接触多层基板。 锥形末端的顶点耦合到接地平面元件，并且金属波导的底侧与多人基板接触并耦合到微带线。

公开(公告)号：US09355991B2

公开(公告)日：2016-05-31

申请号：US14938465

申请日：2015-11-11

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L21/50 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: A method for fabricating an electronic multi-output device. A substrate having a pad and pins is provided. A first chip is provided having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface and the patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. A driver and control chip is attached to the substrate pad adjacent to the first chip. The second terminals of the first and second transistors are connected by discrete first and second gang clips to respective substrate pins. A second chip is provided having a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to attach the first terminals vertically to the first and second gang clips. The third terminals are concurrently attached by discrete gang clips to respective pins. A common clip is attached to the common second terminal and connecting the common clip to a pin.

Abstract translation: 一种制造电子多输出装置的方法。 提供具有焊盘和引脚的基板。 提供第一芯片，其具有集成的第一和第二晶体管，使得晶体管的第一端子在一个芯片表面上合并成公共端子，并且图案化的第二和第三端子在相对的芯片表面上。 公共第一端子附接到衬底垫。 驱动器和控制芯片附接到与第一芯片相邻的衬底焊盘。 第一和第二晶体管的第二端子通过离散的第一和第二组合夹连接到相应的衬底引脚。 提供第二芯片，其具有集成的第三和第四晶体管，使得晶体管的第二端子在一个芯片表面上合并成公共端子。 图案化的第一和第三端子在相对的芯片表面上。 第二芯片被翻转以将第一终端垂直地附接到第一和第二组合夹。 第三端子通过离散的组夹同时附接到相应的引脚。 共同的夹子连接到公共第二端子并将公共夹子连接到销。

公开(公告)号：US09350063B2

公开(公告)日：2016-05-24

申请号：US13854943

申请日：2013-04-01

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Gerd Schuppener ,  Robert Floyd Payne

IPC: H01P3/16 ,  H01Q13/00 ,  H01P3/12 ,  H05K1/02

CPC classification number: H01P3/16 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01P1/04 ,  H01P3/121 ,  H01Q13/00 ,  H05K1/0239 ,  H05K1/024 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09618 ,  H05K2201/10098 ,  Y10T29/49826 ,  Y10T29/49908

Abstract: A dielectric wave guide (DWG) has a dielectric core member having that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured in a non-planer shape for mating with a second DWG having a matching non-planar shaped mating end.

Abstract translation: 电介质波导（DWG）具有具有第一介电常数值的介质芯构件。 围绕介电芯构件的包层具有低于第一介电常数的第二介电常数值。 DWG的配合端构造成非平面形状，用于与具有匹配的非平面形配合端的第二DWG配合。

公开(公告)号：US09306263B2

公开(公告)日：2016-04-05

申请号：US13854939

申请日：2013-04-01

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Eunyoung Seok ,  Baher Haroun

IPC: H01P5/107 ,  H01P3/16 ,  H01P5/08 ,  G02B6/44 ,  H01P11/00 ,  H01P5/00 ,  H01Q1/50 ,  H01Q19/10 ,  H04B1/40 ,  H01Q19/30 ,  H01P3/12

CPC classification number: H01P3/16 ,  G02B6/4416 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01P3/121 ,  H01P3/165 ,  H01P5/00 ,  H01P5/087 ,  H01P5/107 ,  H01P5/184 ,  H01P11/001 ,  H01P11/002 ,  H01Q1/50 ,  H01Q19/108 ,  H01Q19/30 ,  H04B1/40 ,  Y10T29/49016 ,  Y10T29/49826

Abstract: An electronic device has a multilayer substrate that has an interface surface configured for interfacing to a dielectric waveguide. A conductive layer on the substrate is etched to form a dipole antenna disposed adjacent the interface surface to provide coupling to the dielectric waveguide. A reflector structure is formed in the substrate adjacent the dipole antenna opposite from the interface surface.

Abstract translation: 电子设备具有多层基板，该多层基板具有被配置为与电介质波导连接的界面。 蚀刻衬底上的导电层以形成邻近界面表面设置的偶极天线，以提供与介质波导的耦合。 反射器结构形成在与界面表面相对的偶极子天线附近的衬底中。

公开(公告)号：US20160064361A1

公开(公告)日：2016-03-03

申请号：US14938387

申请日：2015-11-11

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L25/065 ,  H01L23/495

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The first chip with its first terminal is tied to the first pad. A second chip with a second transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The second chip with its first terminal is tied to the second pad. The second terminals are connected by a discrete first metal clip and a second metal clip to respective substrate pins. A composite third chip has a third and a fourth transistor integrated so that the first terminals of the transistors are on one chip surface. The second terminals are merged into a common terminal. The patterned third terminals are on the opposite chip surface. The first terminals are vertically attached to the first and second metal clips, respectively. The common terminal is connected by a common clip to a substrate pin.

Abstract translation: 电子多输出装置具有包括第一垫，第二垫和多个销的基板。 具有第一晶体管的第一芯片在一个芯片表面上具有第一端子，在相对的芯片表面上具有第二和第三端子。 第一个芯片与第一个终端绑在第一个焊盘上。 具有第二晶体管的第二芯片在一个芯片表面上具有第一端子，在相对的芯片表面上具有第二和第三端子。 具有第一个终端的第二个芯片与第二个焊盘相连。 第二端子通过离散的第一金属夹和第二金属夹连接到相应的衬底引脚。 复合第三芯片具有集成的晶体管的第一端子在一个芯片表面上的第三和第四晶体管。 第二个终端被合并成一个公共终端。 图案化的第三端子在相对的芯片表面上。 第一端子分别垂直地附接到第一和第二金属夹。 公共端子通过公共夹子连接到基板引脚。

公开(公告)号：US09214415B2

公开(公告)日：2015-12-15

申请号：US14181966

申请日：2014-02-17

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).

Abstract translation: 一种封装的多输出转换器（200），包括具有作为接地端子的芯片焊盘（201）的引线框和包括所述电输入端子（203）的多个引线（202）; 第一FET芯片（同步芯片，220），其源极端子固定到引线框架，并且在其相对表面上与第二漏极端子（222）相邻定位的第一漏极端子（221），漏极端子分别由第一（ 241）和第二（242）金属夹到第一（204）和第二（205）输出引线; 位于第一漏极端子上方的第二FET芯片（控制芯片211），其源极端子附接到第一夹子上; 第三FET芯片（控制芯片212），其垂直地位于第二漏极端子上，其源极端子附接到第二夹子上; 和连接到连接到输入引线（203）的第三金属夹（260）上的第二和第三芯片的漏极端子（213,214）。

公开(公告)号：US09166269B2

公开(公告)日：2015-10-20

申请号：US13907949

申请日：2013-06-02

Applicant: Texas Instruments Incorporated

Inventor： Baher Haroun ,  Juan Alejandro Herbsommer

IPC: H01P1/10 ,  H01P3/16 ,  H01P5/08 ,  G02B6/44 ,  H01P11/00 ,  H01P5/00 ,  H01Q1/50 ,  H01Q19/10 ,  H04B1/40 ,  H01Q19/30 ,  H01P3/12 ,  H01P5/107

CPC classification number: H01P3/16 ,  G02B6/4416 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01P3/121 ,  H01P3/165 ,  H01P5/00 ,  H01P5/087 ,  H01P5/107 ,  H01P5/184 ,  H01P11/001 ,  H01P11/002 ,  H01Q1/50 ,  H01Q19/108 ,  H01Q19/30 ,  H04B1/40 ,  Y10T29/49016 ,  Y10T29/49826

Abstract: A rotatable coupler for dielectric wave guides is described. A first dielectric wave guide (DWG) has an interface surface at a one end of the DWG. A second DWG has a matching interface surface at an end of the second DWG. A rotatable coupling mechanism is coupled to the two DWG ends and is configured to hold the interface surface of the first DWG in axial alignment with the interface surface of the second DWG while allowing the interface surface of the first DWG to rotate axially with respect to the interface surface of the second DWG.

Abstract translation: 描述了用于介质波导的可旋转耦合器。 第一介质波导（DWG）在DWG的一端具有界面。 第二个DWG在第二个DWG的末尾具有匹配的界面。 可旋转的联接机构联接到两个DWG端部并且被配置为保持第一DWG的接口表面与第二DWG的界面表面轴向对准，同时允许第一DWG的界面相对于第二DWG轴向旋转 第二个DWG的界面。

公开(公告)号：US20150295651A1

公开(公告)日：2015-10-15

申请号：US14506639

申请日：2014-10-04

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Benjamin S. Cook

IPC: H04B10/2575 ,  G02B6/036

CPC classification number: G02B6/1221 ,  B29C33/38 ,  B33Y10/00 ,  B33Y80/00 ,  G02B6/036 ,  G02B6/13 ,  G02B6/42 ,  G02B6/4203 ,  H04B10/25

Abstract: A digital system has a dielectric core waveguide that has a longitudinal dielectric core member. The core member has a body portion and a transition region, with a cladding surrounding the dielectric core member. The body portion of the core member has a first dielectric constant. The transition region of the core member has a graduated dielectric constant value that gradually changes from the first dielectric constant value adjacent the body portion to a third dielectric constant.

Abstract translation: 数字系统具有介电芯波导，其具有纵向介质芯构件。 芯构件具有主体部分和过渡区域，其中包围围绕介质芯构件的包层。 芯构件的主体部分具有第一介电常数。 芯部件的过渡区域具有从邻近主体部分的第一介电常数值逐渐变化到第三介电常数的刻度介电常数值。