公开(公告)号：US09634249B2

公开(公告)日：2017-04-25

申请号：US15207979

申请日：2016-07-12

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1608 ,  H01L27/2436 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1691

摘要： A device includes a pillar-shaped insulating layer above a first pillar-shaped semiconductor layer. A resistance-changing film is around an upper portion of the pillar-shaped insulating layer and a lower electrode is around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film. A reset gate insulating film surrounds the resistance-changing film, and a reset gate surrounds the reset gate insulating film.

公开(公告)号：US09620564B2

公开(公告)日：2017-04-11

申请号：US15093981

申请日：2016-04-08

申请人： UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/76 ,  H01L31/062 ,  H01L21/00 ,  H01L21/336 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L21/3105 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/228 ,  H01L21/31051 ,  H01L23/528 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827 ,  H01L43/08 ,  H01L43/12

摘要： A semiconductor device includes four or more first memory cells arranged on a row, the first memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film formed around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film, and a first magnetic tunnel junction storage element formed on the first pillar-shaped semiconductor layer. The semiconductor device further includes a first source line that connects lower portions of the first pillar-shaped semiconductor layers to each other, a first bit line that extends in a direction perpendicular to a direction in which the first gate line extends and that is connected to an upper portion of the first magnetic tunnel junction storage element, and a second source line that extends in a direction perpendicular to a direction in which the first source line extends.

公开(公告)号：US09478545B2

公开(公告)日：2016-10-25

申请号：US14963432

申请日：2015-12-09

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L27/0924 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

摘要： A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate. A first insulating film is around the first and second fin-shaped layers. A first and second pillar-shaped semiconductor layers reside on the first and second fin-shaped layers, respectively. A width of a bottom of the first pillar-shaped semiconductor layer is equal to a width of a top of the first fin-shaped semiconductor layer, and a width of a bottom of the second pillar-shaped semiconductor layer is equal to the width of a top of the second fin-shaped semiconductor layer. First and second gate insulating films and first and second metal gate electrodes reside around the first and second pillar-shaped layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped layers.

摘要翻译： 半导体器件包括在衬底上的第一和第二鳍状半导体层。 第一绝缘膜围绕第一和第二鳍状层。 第一和第二柱状半导体层分别位于第一和第二鳍状层上。 第一柱状半导体层的底部的宽度等于第一鳍状半导体层的顶部的宽度，第二柱状半导体层的底部的宽度等于 第二鳍状半导体层的顶部。 第一和第二栅极绝缘膜和第一和第二金属栅电极分别位于第一和第二柱状层周围。 金属栅极线连接到第一和第二金属栅极，并且在垂直于第一和第二鳍状层的方向上延伸。

公开(公告)号：US09431501B2

公开(公告)日：2016-08-30

申请号：US14744588

申请日：2015-06-19

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L27/085 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/401 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02639 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/762 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/0921 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/7827

摘要： A semiconductor device includes a third first-conductivity-type semiconductor layer on a semiconductor substrate; a first pillar-shaped semiconductor layer formed on the semiconductor substrate and including a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, a second second-conductivity-type semiconductor layer, and a third second-conductivity-type semiconductor layer; a first gate insulating film around the first body region; a first gate around the first gate insulating film; a second gate insulating film around the second body region; a second gate around the second gate insulating film; an output terminal made of a semiconductor and connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer; and a first contact that connects the first gate and the second gate. The second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer are further formed in the output terminal.

摘要翻译： 半导体器件包括在半导体衬底上的第三第一导电型半导体层; 形成在半导体衬底上的第一柱状半导体层，包括第一第一导电型半导体层，第一体区，第二第一导电型半导体层，第一第二导电型半导体层，第 第二体区，第二第二导电型半导体层和第三第二导电型半导体层; 围绕第一体区的第一栅极绝缘膜; 围绕第一栅绝缘膜的第一栅极; 围绕第二体区的第二栅极绝缘膜; 围绕第二栅极绝缘膜的第二栅极; 由半导体制成并与第二第一导电型半导体层和第一第二导电型半导体层连接的输出端子; 以及连接第一栅极和第二栅极的第一接触。 第二第一导电型半导体层和第一第二导电型半导体层进一步形成在输出端子中。

公开(公告)号：US09412938B2

公开(公告)日：2016-08-09

申请号：US15019441

申请日：2016-02-09

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/76 ,  H01L31/113 ,  H01L29/06 ,  H01L21/00 ,  H01L21/336 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1675

摘要： A semiconductor device includes a first pillar-shaped semiconductor layer and a gate insulating film around the first pillar-shaped semiconductor layer. A gate electrode is around the gate insulating film and a gate line is connected to the gate electrode. A first diffusion layer resides in an upper portion of the first pillar-shaped semiconductor layer and a second diffusion layer resides in a lower portion of the first pillar-shaped semiconductor layer. A memory device on the first diffusion layer includes a pillar-shaped phase-change layer and a reset gate insulating film surrounding the pillar-shaped phase-change layer. A reset gate surrounds the reset gate insulating film, where the reset gate functions as a heater, and the pillar-shaped phase-change layer and the reset gate are electrically insulated from each other.

摘要翻译： 半导体器件包括第一柱状半导体层和围绕第一柱状半导体层的栅极绝缘膜。 栅电极在栅极绝缘膜周围，并且栅极线连接到栅电极。 第一扩散层位于第一柱状半导体层的上部，第二扩散层位于第一柱状半导体层的下部。 第一扩散层上的存储器件包括柱状相变层和围绕柱状相变层的复位栅极绝缘膜。 复位栅极围绕复位栅极绝缘膜，其中复位栅极用作加热器，并且柱状相变层和复位栅极彼此电绝缘。

公开(公告)号：US09337319B2

公开(公告)日：2016-05-10

申请号：US14591664

申请日：2015-01-07

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L29/42344 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7855 ,  H01L29/792

摘要： A semiconductor device includes a fin-shaped semiconductor layer disposed on a semiconductor substrate, a first insulating film disposed around the fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer disposed on the fin-shaped semiconductor layer, a first gate insulating film that is disposed around the first pillar-shaped semiconductor layer and includes a charge storing layer, a second gate insulating film disposed around the first pillar-shaped semiconductor layer and at a position higher than the first gate insulating film, a fifth gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, and a first contact electrode surrounding the fifth gate insulating film.

摘要翻译： 一种半导体器件，包括设置在半导体衬底上的鳍状半导体层，围绕所述鳍状半导体层设置的第一绝缘膜，设置在所述鳍状半导体层上的第一柱状半导体层，第一栅极绝缘膜 其设置在第一柱状半导体层周围，并且包括电荷存储层，设置在第一柱状半导体层周围的第二栅极绝缘膜和高于第一栅极绝缘膜的位置，第五栅极绝缘膜包围 第一柱状半导体层的上部和围绕第五栅极绝缘膜的第一接触电极。

公开(公告)号：US09312396B2

公开(公告)日：2016-04-12

申请号：US14837615

申请日：2015-08-27

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L29/7889 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825

摘要： A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the silicon substrate side, a floating gate arranged so as to surround the outer periphery of the channel region with a tunnel insulating film interposed between the floating gate and the channel region, a control gate arranged so as to surround the outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate, and a control gate line electrically connected to the control gate and extending in a predetermined direction. The inter-polysilicon insulating film is interposed between the floating gate and the lower and inner side surfaces of the control gate and between the floating gate and the lower surface of the control gate line.

摘要翻译： 非易失性半导体存储晶体管包括岛状半导体，其具有从硅衬底侧依次形成的源极区，沟道区和漏极区，浮置栅极，以围绕沟道区的外周的方式布置， 插入在所述浮置栅极和所述沟道区域之间的隧道绝缘膜，控制栅极，其布置成围绕所述浮置栅极的外周，所述控制栅极具有介于所述控制栅极和所述浮置栅极之间的多晶硅间绝缘膜，以及控制栅极 线路电连接到控制门并沿预定方向延伸。 多晶硅间绝缘膜介于浮动栅极与控制栅极的下侧和内侧表面之间以及浮动栅极与控制栅极线的下表面之间。

公开(公告)号：US09299825B2

公开(公告)日：2016-03-29

申请号：US14606464

申请日：2015-01-27

申请人： UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/00 ,  H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/40

CPC分类号： H01L29/7788 ,  H01L21/28035 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/32133 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7827

摘要： A method for producing a semiconductor device includes a first step of forming a fin-shaped silicon layer on a silicon substrate using a first resist and forming a first insulating film therearound; and a second step of forming a second insulating film around the fin-shaped silicon layer and etching the second insulating film so as to be left on a side wall of the fin-shaped silicon layer, depositing a third insulating film on the first and second insulating films and the fin-shaped silicon layer, depositing a polysilicon thereon, planarizing a surface thereof, and etching back the polysilicon to expose the third insulating film, forming a second resist, etching the second and third insulating films and then etching the fin-shaped silicon layer and the polysilicon, and removing the second insulating film to form a pillar-shaped silicon layer and a dummy gate formed of the polysilicon.

摘要翻译： 一种制造半导体器件的方法包括：使用第一抗蚀剂在硅衬底上形成鳍状硅层并在其周围形成第一绝缘膜的第一步骤; 以及第二步骤，在所述鳍状硅层周围形成第二绝缘膜，并蚀刻所述第二绝缘膜以留在所述鳍状硅层的侧壁上，在所述第一和第二绝缘膜上沉积第三绝缘膜 绝缘膜和鳍状硅层，在其上沉积多晶硅，使其表面平坦化，并蚀刻多晶硅以暴露​​第三绝缘膜，形成第二抗蚀剂，蚀刻第二和第三绝缘膜， 并且去除第二绝缘膜以形成由多晶硅形成的柱状硅层和虚拟栅极。

公开(公告)号：US09299701B2

公开(公告)日：2016-03-29

申请号：US14743266

申请日：2015-06-18

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/16

CPC分类号： H01L21/823431 ,  B82Y10/00 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/76895 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

摘要： A semiconductor device includes first and second fin-shaped semiconductor layers on a substrate, where the first and second fin-shaped semiconductor layers correspond to the dimension of a sidewall pattern around a dummy pattern. First and second pillar-shaped semiconductor layers reside on the first and second fin-shaped semiconductor layers, respectively. A gate insulating film and metal gate electrode are around underlying gate insulating layers on each fin-shaped semiconductor layer. A metal gate line is connected to the metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped semiconductor layers. Contacts reside on the upper portion of diffusion layers in upper portions of the first and second pillar-shaped semiconductor layers and are directly connected to the diffusion layers.

摘要翻译： 半导体器件在衬底上包括第一和第二鳍状半导体层，其中第一和第二鳍状半导体层对应于围绕虚拟图案的侧壁图案的尺寸。 第一和第二柱状半导体层分别位于第一和第二鳍状半导体层上。 栅极绝缘膜和金属栅极电极在每个鳍状半导体层的下面的栅极绝缘层周围。 金属栅极线连接到金属栅电极并且在垂直于第一和第二鳍状半导体层的方向上延伸。 触点位于第一和第二柱状半导体层的上部的扩散层的上部，并直接连接到扩散层。

公开(公告)号：US09287396B2

公开(公告)日：2016-03-15

申请号：US14690572

申请日：2015-04-20

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45

CPC分类号： H01L29/7827 ,  H01L29/0657 ,  H01L29/0669 ,  H01L29/0692 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a fin-shaped silicon layer on a silicon substrate and a first insulating film around the fin-shaped silicon layer. A pillar-shaped silicon layer resides on the fin-shaped silicon layer. A gate electrode and gate insulating film surround the pillar-shaped silicon layer and a gate line is connected to the gate electrode and extends in a direction orthogonally intersecting the fin-shaped silicon layer. A first diffusion layer resides in an upper portion of the pillar-shaped silicon layer and a second diffusion layer resides in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer.

摘要翻译： 半导体器件包括在硅衬底上的鳍状硅层和围绕鳍状硅层的第一绝缘膜。 柱形硅层位于翅片状硅层上。 栅极电极和栅极绝缘膜围绕柱状硅层，栅极线连接到栅电极，并且在与鳍状硅层正交的方向上延伸。 第一扩散层位于柱状硅层的上部，第二扩散层位于鳍状硅层的上部和柱状硅层的下部。