公开(公告)号：US12070780B2

公开(公告)日：2024-08-27

申请号：US17442326

申请日：2021-06-30

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Xueyu Liang

IPC: B08B1/30 ,  B08B1/12 ,  B08B1/14 ,  B08B3/02 ,  B08B5/04 ,  B08B13/00 ,  H01F7/20

CPC classification number: B08B1/30 ,  B08B1/12 ,  B08B1/143 ,  B08B3/024 ,  B08B5/04 ,  B08B13/00 ,  H01F7/206 ,  B08B2203/0217 ,  B08B2203/027

Abstract: The present application provides a machine cleaning device. The machine cleaning device includes: a guide rail arranged next to a carrying platform of the machine main body, a support slidably mounted on the guide rail, a cleaning component mounted on the support, a driving device connected to the support in a transmission way, and a controller connected to the driving device; and when the cleaning component cleans the top surface of the machine main body, the controller controls the driving device to drive the support to move along the guide rail, so as to drive the cleaning component to clean the top surface of the machine main body in a direction away from the carrying platform. So that unexpected particles are reduced to fall on the carrying platform and contaminate the carrying platform during the cleaning process.

公开(公告)号：US12069859B2

公开(公告)日：2024-08-20

申请号：US17340888

申请日：2021-06-07

Applicant: Changxin Memory Technologies, Inc.

Inventor： Xing Jin

IPC: H10B43/20 ,  G11C7/18 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10

CPC classification number: H10B43/20 ,  G11C7/18 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10

Abstract: A semiconductor structure and a manufacturing method thereof are present. The method includes: forming a first mask layer having an etching window, wherein the first mask layer includes a first mask sublayer formed on the upper surface of bit line structures, and a second mask sublayer located on the upper surface of the first mask sublayer and the upper surface of an inter-layer dielectric layer, the first mask sublayer has the upper surface level with the upper surface of an inter-layer dielectric layer, and has a plurality of strip-shaped patterns extending in a first direction and spaced apart from each other, and the second mask sublayer has a plurality of strip-shaped patterns extending in a second direction and spaced apart from each other; and etching the inter-layer dielectric layer by using the first mask layer as a mask to form a contact hole exposing a surface of a substrate.

公开(公告)号：US12062702B2

公开(公告)日：2024-08-13

申请号：US17445636

申请日：2021-08-23

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Mengmeng Yang ,  Jie Bai

IPC: H01L29/40 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/401 ,  H01L21/28088 ,  H01L21/28158 ,  H01L29/517

Abstract: In a method for manufacturing a semiconductor structure, a substrate is provided; a stack layer is formed on the substrate, the stack layer including an interfacial layer, a high-k dielectric layer and a work function composite layer which are sequentially stacked; a transition layer is formed on the stack layer; and a metal gate layer is formed on the transition layer. The work function composite layer is prepared by a physical vapor deposition process.

公开(公告)号：US12062558B2

公开(公告)日：2024-08-13

申请号：US17446416

申请日：2021-08-30

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Jun Wang

IPC: H01L21/67 ,  G05B19/418 ,  G05B23/02

CPC classification number: H01L21/67276 ,  G05B19/4184 ,  G05B23/0259

Abstract: A treatment method for an OOC action during a semiconductor production process includes: multiple Out Of Control Action Plan IDs (OCAPID) respectively corresponding to multiple semiconductor production process steps and multiple identified contents in one-to-one correspondence with the multiple OCAPIDs are established, and an OOC action checklist including multiple OOC action check items according to the identified contents is established; it is determined whether the OOC action occurs to a wafer subjected to the current semiconductor production process step, and if the OOC action occurs to the wafer, the current OCAPID corresponding to the current semiconductor production process step is automatically obtained, and the wafer is inspected according to the current identified content corresponding to the current OCAPID.

公开(公告)号：US20240265952A1

公开(公告)日：2024-08-08

申请号：US17796745

申请日：2022-04-18

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Xianjun Wu ,  Weibing Shang ,  Xiaoqing Shi

IPC: G11C7/08 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/1096

Abstract: The disclosed data transmission circuit and a memory include a sense amplifier circuit, a first sub-discharge path, a second sub-discharge path, and a discharge adjustment unit. The sense amplifier circuit generate amplified signals based on two terminals. The first sub-discharge path, in the read state, discharges at the first terminal to the discharge terminal based on the first data line signal; the second sub-discharge path, in reading state, discharges at the second terminal to the discharge terminal based on the discharge adjustment signa. The discharge adjustment unit is electrically connected to the second sub-discharge path and the control signal, but is not connected to the first sub-discharge path, and is used for generating the discharge adjustment signal based on the control signal, to adjust the discharge capacity of the second sub-discharge path. The present disclosure improves the anti-interference ability and data transmission efficiency of the data transmission circuit.

公开(公告)号：US12057318B2

公开(公告)日：2024-08-06

申请号：US17448885

申请日：2021-09-25

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Zhonglei Wang

IPC: H01L21/285 ,  H01J37/32 ,  H01L21/311

CPC classification number: H01L21/28568 ,  H01J37/32449 ,  H01L21/31116 ,  H01J2237/332 ,  H01J2237/334

Abstract: A method for forming a film layer includes: a substrate is provided; a pretreatment step is performed, in which the pretreatment step includes providing a reaction source gas, which forms attachment points on the substrate; and a deposition step is performed, in which the reaction source gas is formed into a plasma, which is deposited on the substrate based on the attachment points to form a first film layer.

公开(公告)号：US12051615B2

公开(公告)日：2024-07-30

申请号：US17445400

申请日：2021-08-18

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Mengzhu Qiao

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/76283 ,  H01L21/823481

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, an isolation trench being formed on the substrate; a silicon-rich isolation layer is formed in the isolation trench, the silicon-rich isolation layer covering an inner surface of the isolation trench; and an isolation oxide layer is formed in the isolation trench. The isolation oxide layer fills up the isolation trench.

公开(公告)号：US12048139B2

公开(公告)日：2024-07-23

申请号：US17438436

申请日：2021-06-11

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Sen Li ,  Jun Xia

IPC: H10B12/00

CPC classification number: H10B12/09

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate; forming a first mask layer with a first pattern on the stack; forming a first photoresist layer on the first mask layer; exposing the first photoresist layer, and developing to remove the first photoresist layer on the complete die region; and etching the stack by using the first mask layer on the complete die region and the first photoresist layer on the incomplete die region as masks.

公开(公告)号：US12047069B2

公开(公告)日：2024-07-23

申请号：US17849033

申请日：2022-06-24

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Keqin Huang ,  Kangling Ji

IPC: H03K19/17736 ,  G11C16/04 ,  H03K19/173

CPC classification number: H03K19/17744 ,  G11C16/0425 ,  H03K19/1737 ,  H03K19/1774

Abstract: A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where the first input end is configured to receive high level signal, the second input end is configured to receive low level signal, the control ends are connected to selection unit and the output end is connected to a serial wire, and the selection unit is configured to receive selection signal and at least two branch signals, and is configured to select, based on the selection signal, one of the branch signals and transmit a selected branch signal to the parallel branch; the serial wire, configured to organize signals output by the parallel branches into a serial signal; and a drive unit, connected to the serial wire for enhancing drive capability of the serial wire, where an output end of the drive unit is configured to output the serial signal.

公开(公告)号：US12046321B2

公开(公告)日：2024-07-23

申请号：US17651597

申请日：2022-02-18

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Geyan Liu

IPC: G11C7/10 ,  G11C5/06 ,  G11C11/4063 ,  G11C11/4072

CPC classification number: G11C7/1078 ,  G11C5/06 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4063 ,  G11C11/4072

Abstract: A compilation method includes the following: receiving a signal to be compiled and a resistance matching signal; performing compilation processing on the signal to be compiled to obtain a compilation result signal; and in the case where the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal according to the resistance matching signal to determine a first compiled value.